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bhyve/ioapic: improve the tracking of IRR bit
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Authored by royger on Jan 19 2021, 2:26 PM.

Details

Summary

One common method of EOI'ing an interrupt at the IO-APIC level is to
switch the pin to edge triggering mode and then back into level mode.
That would cause the IRR bit to be cleared and thus further interrupts
to be injected. FreeBSD does indeed use that method if the IO-APIC EOI
register is not supported.

The bhyve IO-APIC emulation code didn't clear the IRR bit when doing
that switch, and was also missing acknowledging the IRR state when
trying to inject an interrupt in vioapic_send_intr.

Diff Detail

Repository
R10 FreeBSD src repository
Lint
Automatic diff as part of commit; lint not applicable.
Unit
Automatic diff as part of commit; unit tests not applicable.

Event Timeline

I tested all 3 ioapic diffs with a FreeBSD 12.2 guest on -current, with MSI/MSI-x disabled to force virtio-net and ahci to use level-triggered legacy IRQs. Some stress testing was done with those devices without any issue.

This revision is now accepted and ready to land.Tue, Feb 2, 8:23 AM