[PowerPC64] hwpmc: add support for POWER8/9 PMCs

[luporl]

Summary

This change adds support for POWER8 and POWER9 PMCs (bare metal and pseries).
All PowerISA 2.07B non-random events are supported.

Implementation was based on that of PPC970.

Test Plan

Patched versions of libpmc (D26113) and pmcstat (D26114) were used to test the hwpmc module with these changes.

Event counting and sampling, in both system and process modes, worked fine.
It was possible to observe event counts while processes were running, collect samples and generate callchain information (from user and kernel space).

[luporl]

This diff has several changes on top of the previous one. The main ones are:

1. Fix overflow handling in counting mode
   
   The machine independent layer of hwpmc expects to deal with 64-bit counters but PowerPC counters are 32-bit, with a range of 31 bits. This can cause issues in counting mode and even a panic, when the PMC overflows and MI layer thinks a negative increment happened.
   
   To deal with these issues, add an extra overflowcnt field to PMC MD struct, in order to simulate 64-bit counters. This is similar to what is done on ARMv7, but with a couple changes, since ARMv7 overflow strategy didn't work:
   
   1- reset overflowcnt only on writes.
   
   2- make overflowcnt a 64-bit field, since PPC PMCs have a 31-bit range and thus needs 33 extra bits to simulate a 64-bit counter.

2. Rename ppcpnv/powernv to power8

3. Factor out common HWPMC PowerPC code
   
   Common code between E500, MPC7XXX, PPC970 and POWER8 was identified and moved to hwpmc_powerpc.c. The initialize method of each processor family now sets up some parameters, to handle small differences between each one and allow several functions to be shared.
   
   These changes were tested only on POWER9 (bare metal and pseries). It would be nice if someone could test them on the other processors.

Also, this diff also depends on D26532 now, to take advantage of PPC 970 PMC SPRs being the standard ones.

[jhibbits]

I like the refactoring!