arm64 armreg.h: fix TCR_TBI1 definition
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	#define TCR_HPD1 (1UL << TCR_HPD1_SHIFT)			#define TCR_HPD1 (1UL << TCR_HPD1_SHIFT)
	#define TCR_HPD0_SHIFT 41			#define TCR_HPD0_SHIFT 41
	#define TCR_HPD0 (1UL << TCR_HPD0_SHIFT)			#define TCR_HPD0 (1UL << TCR_HPD0_SHIFT)
	#define TCR_HD_SHIFT 40			#define TCR_HD_SHIFT 40
	#define TCR_HD (1UL << TCR_HD_SHIFT)			#define TCR_HD (1UL << TCR_HD_SHIFT)
	#define TCR_HA_SHIFT 39			#define TCR_HA_SHIFT 39
	#define TCR_HA (1UL << TCR_HA_SHIFT)			#define TCR_HA (1UL << TCR_HA_SHIFT)
	#define TCR_TBI1_SHIFT 38			#define TCR_TBI1_SHIFT 38
	#define TCR_TBI1 (1UL << TCR_TBI1_SHIFT			#define TCR_TBI1 (1UL << TCR_TBI1_SHIFT)
	#define TCR_TBI0_SHIFT 37			#define TCR_TBI0_SHIFT 37
	#define TCR_TBI0 (1U << TCR_TBI0_SHIFT)			#define TCR_TBI0 (1U << TCR_TBI0_SHIFT)
	#define TCR_ASID_SHIFT 36			#define TCR_ASID_SHIFT 36
	#define TCR_ASID_WIDTH 1			#define TCR_ASID_WIDTH 1
	#define TCR_ASID_16 (1UL << TCR_ASID_SHIFT)			#define TCR_ASID_16 (1UL << TCR_ASID_SHIFT)
	/* Bit 35 is reserved */			/* Bit 35 is reserved */
	#define TCR_IPS_SHIFT 32			#define TCR_IPS_SHIFT 32
	#define TCR_IPS_WIDTH 3			#define TCR_IPS_WIDTH 3
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arm64 armreg.h: fix TCR_TBI1 definitionClosedPublicActions