RISC-V: handle DTB aligned to less than 2MB

[arichardson]

Summary

By default OpenSBI and BBL will pass the DTB at a 2MB-aligned address.
However, by default there are no 2MB aligned regions between the SBI and
the kernel, so we have to choose a 2MB aligned region after the kernel.
OpenSBI defaults to placing the DTB 32MB after the start of the kernel but
this is not sufficient for a kernel with a large MFS embedded.
We could increase this offset to a larger number (e.g. 64/128/256) but that
imposes restrictions on the minimum RAM size.
Another solution would be to place the DTB between OpenSBI and the kernel
at 1MB alignment, but current locore.S code assumes 2MB alignment.

With this change I can now boot on QEMU with an OpenSBI configured to
store the DTB at an offset of 1MB.

See also https://github.com/riscv/opensbi/issues/169

Co-authored-by: Jessica Clarke <[e-mail]>

[mhorne]

sys/riscv/riscv/locore.S

143 ↗

(On Diff #72723)

Could we define something like PTE_PPN_MASK in pte.h and use ~PTE_PPN_MASK here?

[jrtc27]

sys/riscv/riscv/locore.S

143 ↗

(On Diff #72723)

It would have to be per-level, as the top-most PPN in the PTE is bigger than the rest, but yes, that's probably what we want. Maybe there are places in pmap that could benefit from such a constant too.

[mhorne]

sys/riscv/riscv/locore.S

143 ↗

(On Diff #72723)

Yeah good point. It's also complicated by the fact that Sv39 and Sv48 differ in the size of that top-most slot. So I guess you'll need a define for both.

[nick]

Can confirm it works with and without the bootloader adjustments.

[arichardson]

sys/riscv/riscv/locore.S

143 ↗

(On Diff #72723)

@mhorne Can this cleanup be done later? I haven't looked into RISC-V MMU stuff at all, so I'm not sure I know which macros need to be provided.

[mhorne]

sys/riscv/riscv/locore.S

143 ↗

(On Diff #72723)

Sure, that's fine by me.