- Return 2 x 16-bit registers in the correct byte order for a 4-byte read that spands the CMD/STATUS register. This reversal was hiding the capabilities-list, which prevented the MSI capability from being found for XHCI passthru.
- Reorganize MSI/MSI-x config writes so that a 4-byte write at the capability offset would have the read-only portion skipped. This prevented MSI interrupts from being enabled.
Reported and tested by: Anatoli (me at anatoli dot ws)