Use the proper mask reloading sampling PMCs for Core CPUs.

[jhb]

Test Plan

I don't have an older core CPU around to test this on, but this seems
correct from a code reading point of view. The rest of core_intr uses
IAP_* constants and macros, not IAF_*, and the SDM manuals document the
width for the PMCs for Architecture 1 CPUs is the IAP width. IAF doesn't
show up until Architecture 2.

[emaste]

@rstone may have access to suitable hardware

[rstone]

This is an Intel Core processor? I believe that I have access to one of these. Any idea what the symptoms would be?

[jhb]

I think that sampling would not work correctly. In particular, once it reloaded a counter on an interrupt it would write zero to the counter so it would have to wrap all the way around to trigger (whereas it should be writing the equivalent of -65536 by default). I think this means it would probably sample once and then fail to sample again, though it might possibly sample once per context switch. I would see if the number of samples / second for a similar workload is comparable to a later processor.

Can you do 'p core_iaf_width' in kgdb first and verify it is zero and that 'core_iap_width' is not zero after loading hwpmc?

[emaste]

Accepting based on the same analysis as @jhb above; ideally @rstone can test soon.

[rstone]

I am having a horrific time trying to get HEAD installed on one of these systems. Unfortunately support for i386-only systems in our test lab is rotting and I haven't had time to debug the issue yet. :(

[emaste]

Out of curiosity are these 14Ks @rstone? In any case, I'm guessing it makes sense to just go ahead.