Support creating and using arm64 stage 2 pmap

[andrew]

Summary

Add minimal support for creating stage 2 IPA -> PA mappings. For this
we need to:

• Create a new vmid set to allocate a vmid for each Virtual Machine
• Add the missing stage 2 attributes
• Use these in pmap_enter to create a new mapping
• Handle stage 2 faults

The vmid set is based on the current asid set that was generalised in r358328.
It adds a function pointer for bhyve to use when the kernel needs to reset the
vmid set. This will need to call into EL2 and invalidate the TLB.

The stage 2 attributes have been added. To simplify setting these fields two new
functions are added to get the memory type and protection fields. These are slightly
different on stage 1 and stage 2 tables. We then use them in pmap_enter to set the
new level 3 entry to be stored.

The D-cache on all entries is cleaned to the point of coherency. This is to allow
the data to be visible to the VM. To allow for userspace to load code when creating
a new executable entry an invalid entry is created. When the VM tried to use it the
I-cache is invalidated. As the D-cache has already been cleaned this will ensure the
I-cache is synchronised with the D-cache.

When the hardware implements a VPIPT I-cache we need to either have the correct VMID
set or invalidate it from EL2. As the host kernel will have the wrong VMID set we
need to call into EL2 to clean it. For this a second function pointer is added that
is called when this invalidation is needed.

[andrew]

Add a function pointer for invalidation of the icache at EL2

[andrew]

Add the supporting code to use stage 2 entries:

• Add the vmid set
• Allow a stage 2 pmap to be created & activated
• Disable superpage promotion for stage 2 entries as it assumes stage 1
• Add curvmpmap to track the current VM pmap

[andrew]

sys/arm64/arm64/pmap.c

3473–3474 ↗

(On Diff #69136)

I'm not sure this will work. I'll update it to use the valid bit so the entry can't be cached by the TLB. This may also allow for superpage promotion below.

[andrew]

Create an invalid last level page for stage 2 mappings so it won't be affected by ARMv8.1-TTHM

[andrew]

Remove a possible NULL pointer dereference and the position of a PMAP_UNLOCK

[markj]

sys/arm64/arm64/pmap.c

635 ↗

(On Diff #69209)

You might make this an explicit panic().

6302 ↗

(On Diff #69209)

This block is duplicated. Can it be lifted into a subroutine?

sys/arm64/include/pmap.h

165 ↗

(On Diff #69209)

The existing prototypes seem to be alphabetically sorted.

192 ↗

(On Diff #69209)

Is pmap_clean_stage2_tlbi supposed to be exported as well?

[andrew]

Update based on feedback from Mark

[andrew]

Add the missed pmap_clean_stage2_tlbi

[andrew]

Ping?

[markj]

sys/arm64/arm64/pmap.c

3715 ↗

(On Diff #69216)

Why exactly do we prohibit promotion? What happens if a large mapping in a stage2 pmap is created by pmap_enter_l2()?

6248 ↗

(On Diff #69216)

Style: missing space after the switch.

[andrew]

• Add/update comments to help with unobvious code
• Fix a style bug
• Switch back to clearing the AF bit, clearing the valid bit breaks when destroying the pmap

[andrew]

sys/arm64/arm64/pmap.c

3715 ↗

(On Diff #69216)

It's because the current break-before-make code won't work for a stage 2 entry. In the vmm code I'm locking all the vcpus before creating new mappings, however there may be stale TLB entries that need to be invalidated at EL2 and pmap_promote_l2 needs to be taught about this and how to update stage 2 mappings.