I've tested this patch on cores with and without hardware support for accessed flag and dirty state updates. The recently removed printf() calls showed that the Translation Control Registrar is correctly configured.
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I also tested this patch with the following added changes:
diff --git a/sys/arm64/arm64/pmap.c b/sys/arm64/arm64/pmap.c index 7f96431648d..ea394d12ee0 100644 --- a/sys/arm64/arm64/pmap.c +++ b/sys/arm64/arm64/pmap.c @@ -5983,8 +5983,8 @@ pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz ) } } -int -pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far) +static int +_pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far) { pt_entry_t pte, *ptep; register_t intr; @@ -6076,6 +6076,27 @@ pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far) return (rv); } +static SYSCTL_NODE(_debug, OID_AUTO, counters, CTLFLAG_RD, 0, ""); + +static long successes; +SYSCTL_ULONG(_debug_counters, OID_AUTO, successes, CTLFLAG_RD, &successes, 0, ""); + +static long failures; +SYSCTL_ULONG(_debug_counters, OID_AUTO, failures, CTLFLAG_RD, &failures, 0, ""); + +int +pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far) +{ + int rv; + + rv = _pmap_fault(pmap, esr, far); + if (rv == KERN_SUCCESS) + atomic_add_long(&successes, 1); + else + atomic_add_long(&failures, 1); + return (rv); +} + /* * Increase the starting virtual address of the given mapping if a * different alignment might result in more superpage mappings.
The effect of this patch should be a reduction in the number of "successes" on hardware that performs access flag and dirty state updates, and in fact that's what I see. After a "buildworld", the counts are
debug.counters.failures: 214131371 debug.counters.successes: 16036
with this patch applied. In contrast, the counts are
debug.counters.failures: 214137681 debug.counters.successes: 223485437
without hardware access flag and dirty state updates.