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hwpmc : fix perf counter MSR access
Needs ReviewPublic

Authored by shreyankamartya229_gmail.com on Fri, Sep 6, 4:54 PM.

Details

Reviewers
mmacy
markj
mjg
Summary

amd_intr() does not account for the offset (0x200) in the counter MSR address and ends up accessing invalid regions while reading counter value after the 4th counter (0xC001000[8,9,..]) and erroneously updates the counter values for counters [1-4].

Test Plan

Tested on amd64 platform

Diff Detail

Repository
rS FreeBSD src repository
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Event Timeline

shreyankamartya229_gmail.com edited the test plan for this revision. (Show Details)

amd_intr() should only check core pmcs for interrupts since other types of pmcs (L3,DF) cannot generate interrupts.

Newer AMD processors have an NMI latency, due to which pmc NMI's are ignored in certain scenarios such as:
Stopping a pmc ( pcd_stop_pmc() (hwpmc_mod.c)) followed by marking the pmc as free ( pcd_config_pmc( , , NULL)). In this scenario we receive an NMI after the pmc has been marked free and the interrupt ends being ignored.

A similar fix for linux was done here:
https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?id=914123fa39042e651d79eaf86bbf63a1b938dddf

PMCs interrupting at the same time are collapsed into one interrupt. With the current interrupt handler, the majority of samples are missing for one of the event when two such events are used (unhalted_cpu_cycles and retired_intructions). Out of the two, the one which is allocated first reports all the samples while the other one reports negligible numbers.

Adding a fix for NMI latency.
Similar fix done in linux: https://lore.kernel.org/patchwork/patch/1062166/

Although it it did not work for linux due to reasons mentioned here: https://lkml.org/lkml/2019/8/1/796
I think it should work fine on freebsd. Please correct me if I'm wrong.