The change adds routines to promote and demote 2MB superpages. It also
adds support for pmap_enter(psind = 1), described in the commit log
message for r321378. A subsequent commit modifies all of the pmap
routines to handle large mappings appropriately.
The changes are largely adopted from amd64. arm64 has more stringent
requirements around superpage mappings in order to avoid TLB conflict
aborts, and these requirements do not apply to RISC-V, which like amd64
permits TLBs to simultaneously cache 4KB and 2MB translations of a given
page. RISC-V only supports 2 software-defined PTE bits, already used
for PTE_SW_MANAGED and PTE_SW_WIRED, so we do not have an analogue to
amd64's PG_PROMOTED; instead, pmap_remove_l2() always invalidates the
entire 2MB range.
Unlike pmap_remove_pde(), RISC-V's pmap_remove_l2() handles TLB
invalidation.
Note that unlike amd64, RISC-V still has the pvh_global_lock.