RISC-V: Add macros for reading performance counter CSRs

[mhorne063_gmail.com]

Summary

The RISC-V spec defines several performance counter CSRs such as: cycle,
time, instret, hpmcounter(3...31). They are defined to be 64-bits wide
on all RISC-V architectures. On RV64 and RV128 they can be read from a
single CSR. On RV32, additional CSRs (given the suffix "h") are present
which contain the upper 32 bits of these counters, and must be read as
well. (See section 2.8 in the User ISA Spec for full details)

This change adds macros for reading these values safely on any RISC-V
ISA length. Obviously we aren't supporting anything other than RV64
at the moment, but this ensures we won't need to change how we read
these values if we ever do.

[mhorne063_gmail.com]

Hi @markj @br, hope I can bother you to review a couple RISC-V patches. I know there's not a heavy amount of development here but you two appeared to be the most active committers.

I will be looking for further improvements that I can submit, so I appreciate your help and cooperation.

[br]

sys/riscv/include/riscvreg.h

234 ↗

(On Diff #50292)

1. Why do you spin here ?
2. Why do you use t0 in a macro ? (what if t0 is used already outside macro ?)

[mhorne063_gmail.com]

sys/riscv/include/riscvreg.h

234 ↗

(On Diff #50292)

The spin is to ensure that the whole value is read properly, as the thread could be preempted between CSR reads.

t0 is listed as a clobbered register, so the compiler is aware of its use.

[jhb]

sys/riscv/include/riscvreg.h

242 ↗

(On Diff #50292)

Out of an abundance of caution, it might be best to add an outer wrapper layer of parentheses around the value for this macro, that is:

((uint64_t)csr_read(csr))

[mhorne063_gmail.com]

sys/riscv/include/riscvreg.h

242 ↗

(On Diff #50292)

Agreed, it can't hurt to have it. I can update the diff in a few hours.