Change Details

The RISC-V spec defines several performance counter CSRs such as: cycle, time, instret, hpmcounter(3...31). They are defined to be 64-bits wide on all RISC-V architectures. On RV64 and RV128 they can be read from a single CSR. On RV32, additional CSRs (given the suffix "h") are present which contain the upper 32 bits of these counters, and must be read as well. (See section 2.8 in the User ISA Spec for full details) This change adds macros for reading these values safely on any RISC-V ISA length. Obviously we aren't supporting anything other than RV64 right now, but this ensures we won't need to change how we read these values if we ever do.

The RISC-V spec defines several performance counter CSRs such as: `cycle`, `time`, `instret`, `hpmcounter(3...31)`. They are defined to be 64-bits wide on all RISC-V architectures. On RV64 and RV128 they can be read from a single CSR. On RV32, additional CSRs (given the suffix "h") are present which contain the upper 32 bits of these counters, and must be read as well. (See section 2.8 in the User ISA Spec for full details) This change adds macros for reading these values safely on any RISC-V ISA length. Obviously we aren't supporting anything other than RV64 at the moment, but this ensures we won't need to change how we read these values if we ever do.

The RISC-V spec defines several performance counter CSRs such as: `cycle`, `time`, `instret`, `hpmcounter(3...31)`. They are defined to be 64-bits wide on all RISC-V architectures. On RV64 and RV128 they can be read from a single CSR. On RV32, additional CSRs (given the suffix "h") are present which contain the upper 32 bits of these counters, and must be read as well. (See section 2.8 in the User ISA Spec for full details) This change adds macros for reading these values safely on any RISC-V ISA length. Obviously we aren't supporting anything other than RV64 right nowat the moment, but this ensures we won't need to change how we read these values if we ever do.