Fix register definitions

Updated, once clock is enabled in sdhci_fdt, rk_emmcphy_init(void) can be called again to get the clock, etc.

Updated accordingly.

Updated.

Disable phy when enable var is false.

Updated.

Global variable is removed.
Phy id is validated after getting id by phynode_get_id().
When enable var is false it will disable the phy.
Looked both NetBSD and linux sources for delay value:

https://github.com/NetBSD/src/blob/trunk/sys/arch/arm/rockchip/rk_emmcphy.c#L207
https://elixir.bootlin.com/linux/v5.2-rc7/source/drivers/phy/rockchip/phy-rockchip-emmc.c#L204

Rockchip RK3399 TRM V1.3 Part2.pdf says in page 698:

After the DLL control loop reaches steady state a DLL ready signal is generated by the DLL circuits ‘phyctrl_dllrdy’. The time from ‘phyctrl_endll’ to DLL ready signal ‘phyctrl_dllrdy’ varies with the clock frequency. At 200MHz clock frequency the DLL ready delay is 2.56us, at 100MHz clock frequency the DLL ready delay is 5.112us and at 50 MHz clock frequency the DLL ready delay is 10.231us.

Correct the class name when creating phynode, otherwise rk_emmcphy_enable() is never called.

Tried with smaller wait values per frequency respectively.
However it is not working. So added more comments in the code
describing why more safer value would work in any case.