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rS322361: Support for v1.10 (latest) of RISC-V privilege specification.

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br created this revision.Jul 31 2017, 8:03 PM

Herald added a reviewer: ngie. · View Herald TranscriptJul 31 2017, 8:03 PM

Herald added subscribers: emaste, bdrewery. · View Herald Transcript

Replacing all instances of __riscv__ with __riscv seems like a slightly unwelcome inconsistency with other architectures. Is there a reason why this change needs to be made?

andrew added a subscriber: andrew.Jul 31 2017, 8:59 PM

andrew added inline comments.

sys/riscv/riscv/machdep.c
858	Why not make this a compile time check?

lwhsu added a subscriber: lwhsu.Aug 4 2017, 12:02 PM

add CTASSERT(FDT)

In D11800#244666, @ngie wrote:

Replacing all instances of __riscv__ with __riscv seems like a slightly unwelcome inconsistency with other architectures. Is there a reason why this change needs to be made?

So RISC-V is extensible ISA and the idea is to have built-in define per each extension, so together with __riscv we now have some subset of these as well (depends on -march string passed to compiler)

__riscv_compressed
__riscv_atomic
__riscv_mul
__riscv_div
__riscv_muldiv
__riscv_fdiv
__riscv_fsqrt
__riscv_float_abi_soft
__riscv_float_abi_single
__riscv_float_abi_double
__riscv_cmodel_medlow
__riscv_cmodel_medany
__riscv_cmodel_pic
__riscv_xlen == 64

br added inline comments.Aug 6 2017, 8:20 AM

sys/riscv/riscv/machdep.c
858	Good idea, added CTASSERT(FDT) thanks!

If current compilers accept both __riscv__ and __riscv could we first commit that as an independent change?

built-in defines change moved to separate review https://reviews.freebsd.org/D11901

remove sbi.S as well

br added a parent revision: D11901: RISC-V: support for GCC 7.1.Aug 6 2017, 1:30 PM

andrew added inline comments.Aug 7 2017, 3:47 PM

lib/csu/riscv/crti.S
49–50	Why does it need the nop?
sys/conf/ldscript.riscv
9	Why is the `+ 0x200000` needed?

remove nop in crti.S
remove align 2 (set to 0) in crti.S

this helps to build correct code

br added inline comments.Aug 8 2017, 2:28 PM

lib/csu/riscv/crti.S
49–50	The compiler was inserting empty space of 2 bytes (0x0000) which is invalid instruction. Using nop we filling that space with real instruction. But I just updated compiler and things getting worse: nop does not help anymore. It looks like R_RISCV_ALIGN relocation uses 3 bytes and things get unaligned. I removed .align 2 and it now works fine
sys/conf/ldscript.riscv
9	because BBL puts kernel to offset 0x200000 of physical memory. Using same offset in VA space helps us to setup initial mapping and jump to VA space in locore.S. So we have translations like 0xffffffc000200000 -> 0x80200000

remove changes added by accident

o Detect physical memory address kernel loaded to
o Remove offset to kernbase in RISC-V linker script

sort riscv boot params struct

Closed by commit rS322361: Support for v1.10 (latest) of RISC-V privilege specification. (authored by br). · Explain WhyAug 10 2017, 2:18 PM

This revision was automatically updated to reflect the committed changes.

RISC-V privilege architecture update v1.10ClosedPublicActions

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Diff 31673

lib/csu/riscv/crt1.c

lib/csu/riscv/crti.S

lib/libc/riscv/gen/fabs.S

libexec/rtld-elf/riscv/reloc.c

share/mk/bsd.cpu.mk

share/mk/bsd.stand.mk

sys/boot/fdt/dts/riscv/lowrisc.dts

sys/boot/fdt/dts/riscv/qemu.dts

sys/boot/fdt/dts/riscv/rocket.dts

sys/boot/fdt/dts/riscv/spike.dts

sys/conf/files.riscv

sys/conf/kern.mk

sys/conf/ldscript.riscv

sys/riscv/conf/GENERIC

sys/riscv/conf/LOWRISC

sys/riscv/conf/LOWRISC.hints

sys/riscv/conf/QEMU

sys/riscv/conf/ROCKET

sys/riscv/conf/SPIKE

sys/riscv/include/machdep.h

sys/riscv/include/riscvreg.h

sys/riscv/include/sbi.h

sys/riscv/riscv/cpufunc_asm.S

sys/riscv/riscv/exception.S

sys/riscv/riscv/intr_machdep.c

sys/riscv/riscv/locore.S

sys/riscv/riscv/machdep.c

sys/riscv/riscv/nexus.c

sys/riscv/riscv/pmap.c

sys/riscv/riscv/riscv_console.c

sys/riscv/riscv/sbi.S

sys/riscv/riscv/swtch.S

sys/riscv/riscv/timer.c

sys/riscv/riscv/trap.c

sys/riscv/riscv/vm_machdep.c

RISC-V privilege architecture update v1.10
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