SPI-mapped MSI interrupts coming from a controller other than GICv2m need to have their trigger and polarity properly configured.
This patch fixes MSI/MSI-X on Annapurna Alpine platform with GICv2. D7662 is a similar patch for GICv3.
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- rS FreeBSD src repository - subversion
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sys/arm/arm/gic.c | ||
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945 | There is a switch according to struct intr_map_data data type in gic_map_intr() already. So, I would prefer to put INTR_MAP_DATA_MSI case in it. And creation of gic_map_msi() would be nice to be similar to gic_map_fdt() in FDT case. |
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Move the code to a new function gic_map_msi() and call it in gic_map_intr() switch case for MSI. No functional changes.
sys/arm/arm/gic.c | ||
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945 | Thanks for the comment, I added a new revision which changes it - please check if it's what you meant. |
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So, are we done with this change? I'll commit this patch today if no further issues are reported. Thanks.