Currently, gve_rx_alloc_ring_dqo() and gve_tx_alloc_ring_dqo() request
CACHE_LINE_SIZE alignment when allocating DMA memory for the DQO TX/RX
descriptor and completion rings. The device requires stronger alignment
than cache line alignment, which was incidentally being met due to how
the kernel allocates memory. Explicitly meet this requirement by
requesting page aligned memory.
Reviewed-by: Jasper Tran O'Leary <jtranoleary@google.com>
Signed-off-by: Tim Hostetler <thostet@google.com>