est: prevent divide-by-zero in est_msr_info
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Authored by guest-seuros on Wed, Jun 17, 12:44 AM.

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imp
kevans
adrian

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rG021a190c88fc: est: prevent divide-by-zero in est_msr_info

Summary

When hw.est.msr_info=1 is set, est_msr_info() extracts the bus clock
from MSR_PERF_STATUS upper bits. On secondary CPUs, the MSR may
contain zero in the frequency ratio field, causing a
divide-by-zero panic.

Observed in pre Skylake Intel cpu.

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rG FreeBSD src repository

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Build Status

Buildable 73923
Build 70806: arc lint + arc unit

Event Timeline

guest-seuros requested review of this revision.Wed, Jun 17, 12:44 AM

guest-seuros created this revision.

Harbormaster completed remote builds in B73919: Diff 179892.Wed, Jun 17, 12:44 AM

oh interesting, what did you observe this on?

guest-seuros edited the summary of this revision. (Show Details)Wed, Jun 17, 3:22 AM

get rid of the bootverbose change and putit in a different diff, and then i'll approve/land

sys/x86/cpufreq/est.c
1051	you should put this in a different diff. :-)

remove bootverbose gating

Harbormaster completed remote builds in B73923: Diff 179900.Wed, Jun 17, 7:14 AM

guest-seuros added a child revision: D57616: est: gate "not recognized" message behind bootverbose.Wed, Jun 17, 8:06 AM

I can't find where this is documented - all of the SDMs I've looked at so far describe IA32_PERF_STATUS but do not cover the format of the register above bit 31.

This revision is now accepted and ready to land.Wed, Jun 17, 2:49 PM

Closed by commit rG021a190c88fc: est: prevent divide-by-zero in est_msr_info (authored by guest-seuros, committed by adrian). · Explain WhyWed, Jun 17, 2:51 PM

This revision was automatically updated to reflect the committed changes.

adrian added a commit: rG021a190c88fc: est: prevent divide-by-zero in est_msr_info.