est: prevent divide-by-zero in est_msr_info

[guest-seuros]

Summary

When hw.est.msr_info=1 is set, est_msr_info() extracts the bus clock
from MSR_PERF_STATUS upper bits. On secondary CPUs, the MSR may
contain zero in the frequency ratio field, causing a
divide-by-zero panic.

Observed in pre Skylake Intel cpu.

[adrian]

oh interesting, what did you observe this on?

[adrian]

get rid of the bootverbose change and putit in a different diff, and then i'll approve/land

sys/x86/cpufreq/est.c

1051

you should put this in a different diff. :-)

[guest-seuros]

remove bootverbose gating

[adrian]

I can't find where this is documented - all of the SDMs I've looked at so far describe IA32_PERF_STATUS but do not cover the format of the register above bit 31.