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Allwinner A31 clocks driver
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Authored by manu_bidouilliste.com on Feb 19 2016, 2:27 AM.
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Details

Summary

Add driver for A31 clock module.
Only SD and GMAC is currently supported.
Modify thoses drivers to enable the correct clock based on machdep data.

Diff Detail

Repository
rS FreeBSD src repository - subversion
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Lint Passed
Unit
No Test Coverage
Build Status
Buildable 2665
Build 2684: arc lint + arc unit

Event Timeline

manu_bidouilliste.com retitled this revision from to Allwinner A31 clocks driver.
manu_bidouilliste.com updated this object.
manu_bidouilliste.com edited the test plan for this revision. (Show Details)
manu_bidouilliste.com set the repository for this revision to rS FreeBSD src repository - subversion.
manu_bidouilliste.com added a project: ARM.
sys/arm/allwinner/a20/a20_if_dwc.c
65

Tab after int?

sys/arm/allwinner/a31/a31_clk.c
210

What units is freq in?

sys/arm/allwinner/a31/a31_clk.c
210

In Hz, the value passed is the clock one in struct mmc_ios

Add I2c.
Correct two register name (APB1/2 versus APB0/1).

GMAC clock was missing some bits so it didn't worked.

Does this build? You added a file, but it's not in any of the files.* files.

Add ifdef on SOC_ALLWINNER_A31/S to a31 clk function.

Does this build? You added a file, but it's not in any of the files.* files.

Now it does.
The files.a31 will come later on a new review with a generic ALLWINNER kernel config.

sys/arm/allwinner/a10_mmc.c
175–179

This should be under #if defined(SOC_ALLWINNER_A10) || ...

187

You should add a default case above to set clk to an invalid value to get into here.

824

Set error in the default case.

sys/arm/allwinner/a31/a31_clk.c
63

You don't need bst or bsh, you can use bus_read_4((sc)->res, ...) and bus_write_4((sc)->res, ...)

144–145

How long are these lines?

sys/dev/iicbus/twsi/a10_twsi.c
101–103

Only needed on A10?

Add ifdefs for A10/A20 and default case if we don't know which SoC we are running on.
Fix a few style(9) errors.

sys/arm/allwinner/a10_mmc.c
828

As this value is returned it should be positive and code from errno, maybe ENXIO.

sys/arm/allwinner/a31/a31_clk.c
145

Put the >> at the end of the line. The convention is "... put the operator at the end of the line."

Return ENXIO for mmcbr_update_ios
Fix style(9) in a31_clk.c

jmcneill_invisible.ca added inline comments.
sys/arm/allwinner/a31/a31_clk.c
203

Missing software reset here (AHB1_RST_REG0). Shouldn't rely on U-Boot to set this up for us as the power on default for all of these peripherals is to have the reset line asserted.

276

Missing software reset (APB2_RST_REG)

sys/arm/allwinner/a31/a31_clk.c
95

Are these used anywhere?

133

When modifying a PLL on A31, there is a lock status bit in PLL<n>_CFG_REG. It will read back as 1 when the PLL becomes stable. You should wait for this bit to set before returning whenever you make a change.

181

I think you need to set A31_CCM_AHB1_RST_REG0_GMAC here, not clear it. 0 is reset asserted, 1 is reset de-asserted.

272

magic number

sys/arm/allwinner/a31/a31_clk.h
149

#define<tab>

sys/arm/allwinner/a31/a31_clk.c
95

I don't think so, I blindly ported the a10 clk driver as a base.

sys/arm/allwinner/a31/a31_clk.c
272

And it's not even needed, a31 doesn't have TWI4 ...

Add soft reset for TWI and SD.
Fix style(9) and remove unused code.

sys/arm/allwinner/a31/a31_clk.c
127

In case the PLL doesn't lock, there should be a timeout here.

sys/arm/allwinner/a31/a31_clk.c
136

I think you want if (i == PLL6_TIMEOUT)

This revision is now accepted and ready to land.Feb 26 2016, 1:38 PM
This revision was automatically updated to reflect the committed changes.