Allwinner A31 clocks driver

[manu_bidouilliste.com]

Summary

Add driver for A31 clock module.
Only SD and GMAC is currently supported.
Modify thoses drivers to enable the correct clock based on machdep data.

[andrew]

sys/arm/allwinner/a20/a20_if_dwc.c

65 ↗

(On Diff #13465)

Tab after int?

sys/arm/allwinner/a31/a31_clk.c

209 ↗

(On Diff #13465)

What units is freq in?

[manu_bidouilliste.com]

sys/arm/allwinner/a31/a31_clk.c

209 ↗

(On Diff #13465)

In Hz, the value passed is the clock one in struct mmc_ios

[manu_bidouilliste.com]

Add I2c.
Correct two register name (APB1/2 versus APB0/1).

[manu_bidouilliste.com]

GMAC clock was missing some bits so it didn't worked.

[andrew]

Does this build? You added a file, but it's not in any of the files.* files.

[manu_bidouilliste.com]

Add ifdef on SOC_ALLWINNER_A31/S to a31 clk function.

[manu_bidouilliste.com]

In D5339#115605, @andrew wrote:

Does this build? You added a file, but it's not in any of the files.* files.

Now it does.
The files.a31 will come later on a new review with a generic ALLWINNER kernel config.

[andrew]

sys/arm/allwinner/a10_mmc.c

175–179 ↗

(On Diff #13696)

This should be under #if defined(SOC_ALLWINNER_A10) || ...

187 ↗

(On Diff #13696)

You should add a default case above to set clk to an invalid value to get into here.

820 ↗

(On Diff #13696)

Set error in the default case.

sys/arm/allwinner/a31/a31_clk.c

62 ↗

(On Diff #13696)

You don't need bst or bsh, you can use bus_read_4((sc)->res, ...) and bus_write_4((sc)->res, ...)

143–144 ↗

(On Diff #13696)

How long are these lines?

sys/dev/iicbus/twsi/a10_twsi.c

100–102 ↗

(On Diff #13696)

Only needed on A10?

[manu_bidouilliste.com]

Add ifdefs for A10/A20 and default case if we don't know which SoC we are running on.
Fix a few style(9) errors.

[andrew]

sys/arm/allwinner/a10_mmc.c

828 ↗

(On Diff #13739)

As this value is returned it should be positive and code from errno, maybe ENXIO.

sys/arm/allwinner/a31/a31_clk.c

144 ↗

(On Diff #13739)

Put the >> at the end of the line. The convention is "... put the operator at the end of the line."

[manu_bidouilliste.com]

Return ENXIO for mmcbr_update_ios
Fix style(9) in a31_clk.c

[jmcneill_invisible.ca]

sys/arm/allwinner/a31/a31_clk.c

202 ↗

(On Diff #13741)

Missing software reset here (AHB1_RST_REG0). Shouldn't rely on U-Boot to set this up for us as the power on default for all of these peripherals is to have the reset line asserted.

275 ↗

(On Diff #13741)

Missing software reset (APB2_RST_REG)

[jmcneill_invisible.ca]

sys/arm/allwinner/a31/a31_clk.c

94 ↗

(On Diff #13741)

Are these used anywhere?

132 ↗

(On Diff #13741)

When modifying a PLL on A31, there is a lock status bit in PLL<n>_CFG_REG. It will read back as 1 when the PLL becomes stable. You should wait for this bit to set before returning whenever you make a change.

180 ↗

(On Diff #13741)

I think you need to set A31_CCM_AHB1_RST_REG0_GMAC here, not clear it. 0 is reset asserted, 1 is reset de-asserted.

271 ↗

(On Diff #13741)

magic number

sys/arm/allwinner/a31/a31_clk.h

148 ↗

(On Diff #13741)

#define<tab>

[manu_bidouilliste.com]

sys/arm/allwinner/a31/a31_clk.c

94 ↗

(On Diff #13741)

I don't think so, I blindly ported the a10 clk driver as a base.

[manu_bidouilliste.com]

sys/arm/allwinner/a31/a31_clk.c

271 ↗

(On Diff #13741)

And it's not even needed, a31 doesn't have TWI4 ...

[manu_bidouilliste.com]

Add soft reset for TWI and SD.
Fix style(9) and remove unused code.

[jmcneill_invisible.ca]

sys/arm/allwinner/a31/a31_clk.c

127 ↗

(On Diff #13752)

In case the PLL doesn't lock, there should be a timeout here.

[manu_bidouilliste.com]

Add timeout to pll6_enable.

[jmcneill_invisible.ca]

sys/arm/allwinner/a31/a31_clk.c

135 ↗

(On Diff #13787)

I think you want if (i == PLL6_TIMEOUT)

[manu_bidouilliste.com]

Fix if condition.