Add driver for A31 clock module.
Only SD and GMAC is currently supported.
Modify thoses drivers to enable the correct clock based on machdep data.
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Event Timeline
sys/arm/allwinner/a31/a31_clk.c | ||
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210 | In Hz, the value passed is the clock one in struct mmc_ios |
Now it does.
The files.a31 will come later on a new review with a generic ALLWINNER kernel config.
sys/arm/allwinner/a10_mmc.c | ||
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175–179 | This should be under #if defined(SOC_ALLWINNER_A10) || ... | |
187 | You should add a default case above to set clk to an invalid value to get into here. | |
820 | Set error in the default case. | |
sys/arm/allwinner/a31/a31_clk.c | ||
62 | You don't need bst or bsh, you can use bus_read_4((sc)->res, ...) and bus_write_4((sc)->res, ...) | |
143–144 | How long are these lines? | |
sys/dev/iicbus/twsi/a10_twsi.c | ||
100–102 | Only needed on A10? |
Add ifdefs for A10/A20 and default case if we don't know which SoC we are running on.
Fix a few style(9) errors.
sys/arm/allwinner/a31/a31_clk.c | ||
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95 | Are these used anywhere? | |
133 | When modifying a PLL on A31, there is a lock status bit in PLL<n>_CFG_REG. It will read back as 1 when the PLL becomes stable. You should wait for this bit to set before returning whenever you make a change. | |
181 | I think you need to set A31_CCM_AHB1_RST_REG0_GMAC here, not clear it. 0 is reset asserted, 1 is reset de-asserted. | |
272 | magic number | |
sys/arm/allwinner/a31/a31_clk.h | ||
149 | #define<tab> |
sys/arm/allwinner/a31/a31_clk.c | ||
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95 | I don't think so, I blindly ported the a10 clk driver as a base. |
sys/arm/allwinner/a31/a31_clk.c | ||
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272 | And it's not even needed, a31 doesn't have TWI4 ... |
sys/arm/allwinner/a31/a31_clk.c | ||
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128 | In case the PLL doesn't lock, there should be a timeout here. |
sys/arm/allwinner/a31/a31_clk.c | ||
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136 | I think you want if (i == PLL6_TIMEOUT) |