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Add support for SPI-mapped MSI interrupts outside of GICv2m
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Authored by mst_semihalf.com on Aug 29 2016, 7:39 PM.

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Summary

SPI-mapped MSI interrupts coming from a controller other than GICv2m need to have their trigger and polarity properly configured.
This patch fixes MSI/MSI-X on Annapurna Alpine platform with GICv2. D7662 is a similar patch for GICv3.

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rS FreeBSD src repository
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Event Timeline

mst_semihalf.com retitled this revision from to Add support for SPI-mapped MSI interrupts outside of GICv2m.
mst_semihalf.com updated this object.
mst_semihalf.com edited the test plan for this revision. (Show Details)
mst_semihalf.com added reviewers: zbb, wma, imp, ian.
mst_semihalf.com set the repository for this revision to rS FreeBSD src repository.
mst_semihalf.com added a subscriber: ARM.
skra added a subscriber: skra.Aug 31 2016, 9:21 AM
skra added inline comments.
sys/arm/arm/gic.c
917 ↗(On Diff #19799)

There is a switch according to struct intr_map_data data type in gic_map_intr() already. So, I would prefer to put INTR_MAP_DATA_MSI case in it. And creation of gic_map_msi() would be nice to be similar to gic_map_fdt() in FDT case.

Move the code to a new function gic_map_msi() and call it in gic_map_intr() switch case for MSI. No functional changes.

sys/arm/arm/gic.c
917 ↗(On Diff #19799)

Thanks for the comment, I added a new revision which changes it - please check if it's what you meant.

wma accepted this revision.Sep 5 2016, 6:51 AM
wma edited edge metadata.

So, are we done with this change? I'll commit this patch today if no further issues are reported. Thanks.

This revision is now accepted and ready to land.Sep 5 2016, 6:51 AM
This revision was automatically updated to reflect the committed changes.