sdhci_fsl: add ACPI front-end for NXP Layerscape eSDHC (NXP0003)

[yarshure_gmail.com]

Summary

Refactor the FDT-only sdhci_fsl driver into a bus-agnostic base class
(DEFINE_CLASS_0 "sdhci_fsl") plus FDT and ACPI subclasses, mirroring
sdhci_xenon. A shared sdhci_fsl_attach_common() does the controller
bring-up; each front-end supplies the bus-specific bits (soc_data, base
clock, endianness, mmc host properties, card-detect).

The new ACPI front-end (sdhci_fsl_acpi.c) matches _HID NXP0003, reads the
base clock from the _DSD "clock-frequency" property (there is no FDT clock
framework under ACPI), and brings up the eSDHC controllers described by
UEFI/EDK2 firmware. On a SolidRun LX2160A CEX7 booting via EDK2 this
exposes the SD/TF card (/dev/mmcsd0) and eMMC (/dev/mmcsd1) that were
previously invisible because no driver matched NXP0003.

• New sdhci_fsl.h: shared softc, soc_data and DECLARE_CLASS(sdhci_fsl_driver).
• sdhci_fsl_fdt.c: split attach into an FDT prologue + bus-agnostic sdhci_fsl_attach_common(); base class + FDT subclass; declare the mmc bridge on the shared "sdhci_fsl" devclass; guard get_ro for the no-GPIO (ACPI) case.
• sdhci_fsl_acpi.c: NXP0003 ACPI binding; base clock from _DSD; generic card-present; mark the slot non-removable (eSDHC present-state card detect is unreliable); cap to high speed pending UHS tuning support.

Developed with AI assistance; the design was reviewed by hand and the
driver was hardware-tested (see Test Plan).

MFC after: 2 weeks

Test Plan

Hardware-tested on a SolidRun HoneyComb / CEX7 (LX2160A) booting via
EDK2/UEFI (ACPI). Before this change nothing matched _HID NXP0003, so the
eSDHC controllers were unattached; after it both slots probe and come up:

mmc0:   <MMC/SD bus> ... on sdhci_fsl_acpi0
mmcsd0: <MMCHC ...>       (SD/TF card)
mmc1:   <MMC/SD bus> ... on sdhci_fsl_acpi1
mmcsd1: <MMCHC ...>       (eMMC)

/dev/mmcsd0 and /dev/mmcsd1 read and write correctly (~23 MB/s read).

The FDT path is preserved unchanged -- the refactor only splits the
existing sdhci_fsl_attach() into an FDT prologue plus a bus-agnostic
sdhci_fsl_attach_common(), mirroring sdhci_xenon's base/FDT/ACPI split.
It has not been re-tested on an FDT-booted board; a smoke test there is
welcome.

Two ACPI-specific choices worth a look: the base clock is read from the
_DSD "clock-frequency" property (no FDT clock framework under ACPI), and
the slot is marked non-removable + capped to high speed (eSDHC
present-state card detect is unreliable; UHS tuning is future work).

[yarshure_gmail.com]

Re-uploaded with full context (git diff -U999999).