Move to 4 level page tables

[andrew]

Summary

This adds support for 4 level pagetables. To help this it adds two functions
to find the lowest table level, and lowest block/page level. It is expected
this will be useful later to support superpages.

The kernel address space has been kept identical for now, however I epxect
to move memory around later to support a larger DMAP region.

This patch is mostly extending the existing code to use the extra level.
It's not quire ready to be committed, there are a few bits in locore.S that
still need a cleanup, but the other parts are ready for feedback.

Test Plan

I've run stress2 tests on the ThunderX in the Sentex cluster.
I don't think the issues I'm seeing there are due to the patch.

[andrew]

sys/arm64/arm64/locore.S

90–93 ↗

(On Diff #14551)

This comment needs to be fixed

468–493 ↗

(On Diff #14551)

This was used early on, it's probably unneeded now if we stick with a 48-bit address space.

[andrew]

sys/arm64/arm64/vm_machdep.c

87 ↗

(On Diff #14551)

Should rename, it's not a l1 address anymore.

[andrew]

• Finish locore.S
• Rename pcb_l1addr

[kib]

sys/arm64/arm64/locore.S

619 ↗

(On Diff #14709)

Is this comment still valid ?

sys/arm64/arm64/pmap.c

921 ↗

(On Diff #14709)

Assert that the pte type is correct, for non-NULL pte ? Same for two more functions below.

1329 ↗

(On Diff #14709)

deadc0de/deadbeef is spiffy, but vm_page_alloc() does not look at the value for NULL object. It might be slightly faster to use zero.

1404 ↗

(On Diff #14709)

Why use literal 9 there ? Isn't it something like L0SHIFT - L1SHIFT ?

[andrew]

sys/arm64/arm64/pmap.c

921 ↗

(On Diff #14709)

What do you mean by pte type? pmap_pte will only return an entry that contains a page or block map. Both of these are the final level and will point at the physical address for the given virtual address.

The comment above is now stale & will be updated.

[kib]

sys/arm64/arm64/pmap.c

921 ↗

(On Diff #14709)

I mean the value of two lowest bits in the pte. Basically, what you said in the first sentence of your reply, expressed as an assert.

[andrew]

Update based on feedback from @kib

[andrew]

Fix format strings so it builds (still need to test)

[andrew]

I changed link_l1_pagetable when it should have been link_l0_pagetable, fix this
Tested on qemu

[kib]

BTW, I suspect that pv_global_lock is not needed on arm64 at all. On amd64 it is still required because we have to issue IPIs for invalidation and delay them as much as possible. With the synchronous and coherent TLB invalidation I _think_ that the issues which are prevented right now by pv_global_lock on amd64, cannot happen on arm64.