msun/x86: convert rest of the extern inline fenv functions to proper linkage
namely
fegetexceptflag(3)
fetestexcept(3)
fesetround(3)
fegetround(3)
fesetenv(3)
Same as it was done in f39754d51b7dc65c4cf9f for feclearexcept(3).
PR: 277958
msun/aarch64: convert fenv functions to proper linkage
namely
fegetexceptflag(3)
fesetexceptflag(3)
feraiseexcept(3)
fetestexcept(3)
fegetround(3)
fesetround(3)
fegetenv(3)
feholdexcept(3)
fesetenv(3)
feupdateenv(3)
feenableexcept(3)
fedisableexcept(3)
fegetexcept(3)
PR: 277958
msun/riscv: convert fenv functions to proper linkage
namely
fegetexceptflag(3)
fesetexceptflag(3)
feraiseexcept(3)
fetestexcept(3)
fegetround(3)
fesetround(3)
fegetenv(3)
feholdexcept(3)
fesetenv(3)
feupdateenv(3)
feenableexcept(3)
fedisableexcept(3)
fegetexcept(3)
PR: 277958
msun/powerpc: convert fenv functions to proper linkage
namely
fegetexceptflag(3)
fesetexceptflag(3)
feraiseexcept(3)
fetestexcept(3)
fegetround(3)
fesetround(3)
fegetenv(3)
feholdexcept(3)
fesetenv(3)
feupdateenv(3)
feenableexcept(3)
fedisableexcept(3)
fegetexcept(3)
PR: 277958
msun/arm: convert fenv functions to proper linkage
namely
fegetexceptflag(3)
fesetexceptflag(3)
feraiseexcept(3)
fetestexcept(3)
fegetround(3)
fesetround(3)
fegetenv(3)
feholdexcept(3)
fesetenv(3)
feupdateenv(3)
feenableexcept(3)
fedisableexcept(3)
fegetexcept(3)
PR: 277958
msun: remove requirement to have C99 inline semantic
The 'extern inline' usage is removed.
PR: 277958Details
- Reviewers
dim emaste andrew - Commits
- rGd15733065c42: msun: remove requirement to have C99 inline semantic
rG70674434e242: msun/arm: convert fenv functions to proper linkage
rGe4505a58a77f: msun/powerpc: convert fenv functions to proper linkage
rG6b89f5360f84: msun/riscv: convert fenv functions to proper linkage
rG3a01e1e1a50c: msun/aarch64: convert fenv functions to proper linkage
rG5bc64b7d417d: msun/x86: convert rest of the extern inline fenv functions to proper linkage
Diff Detail
- Repository
- rG FreeBSD src repository
- Lint
Lint Not Applicable - Unit
Tests Not Applicable
Event Timeline
The status of fegetexcept, feenableexcept, and fedisableexcept and their relationship to __BSD_VISIBLE seems to be rather variable. Some of that variability may be incorrect and other parts expected. I just note the variability itself. A quick look seemed to show:
aarch64/fenv.c does not provide any external/exportable definitions for those.
aarch64/fenv.h has just __BSD_VISIBLE conditional __fenv_static based definitions, nothing for external/exportable support.
arm/fenv.c has definitions not conditional on __BSD_VISIBLE. fegetexcept is exported, unlike for the others. There is no use of weak references.
arm/fenv.h has __BSD_VISIBLE conditional external/exportable-supported based code, including for fegetexcept.
arm/fenv.h has fegetexcept for __ARM_PCS_VFP both inside and outside __BSD_VISIBLE.
powerpc/fenv.h has feenableexcept and fedisableexcept set up for exportable and conditional on __BSD_VISIBLE but fegetexcept is just for the __fenv_static definition.
powerpc/fenv.c has unconditional feenableexcept and fedisableexcept and no fegetexcept. Thre is no use of weak references.
riscv is like powerpc.
x86/fenv.h has the __BSD_VISIBLE conditionality but does not have static implementations of feenableexcept and fedisableexcept.
i387/fenv.c has unconditional feenableexcept and fedisableexcept with weak reference indicated and does not have fegetexcept.
amd64/fenv.c does that as well.
I have no idea why it grown this way, and what was the rationale of the arch maintainers when it did.
I am only interested in re-checking that my patch does not change the current state there. If somebody do it, I would appreciate.
I have submitted https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=294143 "Variability in defining fegetexcept, feenableexcept, and fedisableexcept across platforms" via mostly quoting your comment that contained my comment as well.