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Enable GICv3 system register interface
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Authored by mst_semihalf.com on Feb 22 2016, 4:09 PM.
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Details

Summary

Set SRE bit in ICC_SRE_EL2 register.

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rS FreeBSD src repository - subversion
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mst_semihalf.com retitled this revision from to Enable GICv3 system register interface.
mst_semihalf.com updated this object.
mst_semihalf.com edited the test plan for this revision. (Show Details)
mst_semihalf.com added reviewers: andrew, imp, wma.
mst_semihalf.com set the repository for this revision to rS FreeBSD src repository - subversion.
mst_semihalf.com added a subscriber: arm64.
sys/arm64/arm64/locore.S
268 ↗(On Diff #13610)

Any reason these shouldn't be combined into one orr?

sys/arm64/arm64/locore.S
268 ↗(On Diff #13610)

As it turns out, ARMv8 has special requirements regarding logical immediates and this particular combination of bits does not qualify.

wma edited edge metadata.

Just tested on ThunderX and is working.

This revision is now accepted and ready to land.Feb 23 2016, 7:39 AM

For what purpose is this patch? I can see it enables the system register interface, but why does it need to be enabled?

For what purpose is this patch? I can see it enables the system register interface, but why does it need to be enabled?

It is always needed for ARM64 as we use the system registers, not memory-mapped ones. I guess in case of ThunderX the bit was already set by the bootloader. In the case of Alpine V2 it was not, which resulted in an error in GIC attach.

This revision was automatically updated to reflect the committed changes.