Implement single stepping on arm64 by setting the single step bits on the processor and debug state registers. We set mdscr on each context switch, this should be replaced by a flag to mark when this bit needs to be set.
Details
Details
- Reviewers
kib - Group Reviewers
arm64 - Commits
- rS295142: Implement single stepping on arm64. We need to set the single step bits in
Diff Detail
Diff Detail
- Repository
- rS FreeBSD src repository - subversion
- Lint
Lint Not Applicable - Unit
Tests Not Applicable
Event Timeline
| sys/arm64/arm64/swtch.S | ||
|---|---|---|
| 72 ↗ | (On Diff #11816) | I didn't mean to update this comment, it was part of a previous iteration & will be reverted. |
Comment Actions
The implementation looks fine WRT to my limited amount of understanding of the spec.
My real questions are about the specification:
- Why is the single-stepping state is recorded in the global CPU (PE) control register instead of the context-switched registers, e.g. cpsr/spsr ? We have to add special register accesses to context switch.
- What does the PSTATE.SS bit designates ? Or rather, what is supposed the OS to do differently when exception handler is entered and sprs.ss == 0 or 1 ?