riscv: use counter(9) for pmap counters

[mhorne]

Summary

It is more natural for these values which are infrequently read, but may be frequently updated.

[markj]

I was about to comment that other pmaps still use atomics for these counters, but it seems that amd64's also been using counter(9) for a while. I'm a bit skeptical that that's really necessary (except perhaps for p_failures), but it doesn't have much downside either. It would be nice to make at least arm64 consistent.

[alc]

In D45761#1044534, @markj wrote:

I was about to comment that other pmaps still use atomics for these counters, but it seems that amd64's also been using counter(9) for a while. I'm a bit skeptical that that's really necessary (except perhaps for p_failures), but it doesn't have much downside either. It would be nice to make at least arm64 consistent.

I share your skepticism for the L2 counters, but I see no real harm in this change. Similarly, I would have no objections to making the same change on arm64. On arm64, we are using counter(9) for 64KB pages, where the counts are typically two orders of magnitude larger.

[alc]

Does anyone know if any real riscv hardware implements their extension that supports additional page sizes, particularly, 64KB?