riscv stage2 pmap support

[br]

Summary

Add basic Stage2 support (guest physical to host physical)

RISC-V hypervisor spec[1] extends top page table directory from 4K page to 16K page making total addressable memory 1petabyte (4x256TB).
The rest of page table system (including PTE format) is identical.

I am not sure if that makes any sense to us to support all of that space since our VM layout limits user VA space to 128TB.

(If some one want I can try to support all that space, but that could add a mess into pmap.c since NUL2E, NUL1E, NUL0E defines have to be converted into macroses, i.e. NUL2E(pmap) depending on stage could give different bounds)

1. https://five-embeddev.com/riscv-priv-isa-manual/Priv-v1.12/hypervisor.html

Test Plan

Tested on unmodified Spike running Bhyve with 2.5gb of memory

[mhorne]

No objection if you want to commit this now. I agree it is unimportant to support the full address space, at present.

sys/riscv/riscv/pmap.c

1353

[jrtc27]

The rest of page table system (including PTE format) is identical.

That's not entirely true; the G bit exists but is reserved. Having said that I don't think we currently set it? (Though there is code to inspect and preserve it in places)

[br]

In D45481#1037696, @jrtc27 wrote:

The rest of page table system (including PTE format) is identical.

That's not entirely true; the G bit exists but is reserved. Having said that I don't think we currently set it? (Though there is code to inspect and preserve it in places)

right, we will need to support hypervisor memory-management fence instructions (and manage address space/VM IDs etc). I will put this into TODO list.

[br]

sys/riscv/riscv/pmap.c

1353

that is intentional to fit into 80 characters line

[br]

rename variable mtop to m

[mhorne]

In D45481#1037849, @br wrote:

In D45481#1037696, @jrtc27 wrote:

The rest of page table system (including PTE format) is identical.

That's not entirely true; the G bit exists but is reserved. Having said that I don't think we currently set it? (Though there is code to inspect and preserve it in places)

right, we will need to support hypervisor memory-management fence instructions (and manage address space/VM IDs etc). I will put this into TODO list.

FYI I have some old patches for the G bit, but it needs rebasing. This will come after Svpbmt.