arm64/gicv3: correct the size of the distributor mapping

[mhorne]

Summary

Use the GICD_SIZE macro (0x10000), which is half the size of the current
fixed-sized mapping (128 * 1024 == 0x20000).

In ARM64 Hyper-V instances, it seems the Distributor's registers are
located immediately preceding a range of physical memory in the bus
address space. Thus, when ram0 is attaching and attempts to reserve
SYS_RES_MEMORY resources corresponding to its physmem ranges, it fails,
because the first 0x10000 bytes of this range are already owned by gic0.

PR: 270415

Test Plan

This was done by code inspection; I have no way to test this. I also had a hard time finding documentation on the GIC register map, but the GICD_* definitions in gic_v3_reg.h suggest this size is correct.

Hopefully @whu or @kevans can report on if it fixes the observed boot-time panic.

---

Distilled from the PR, the following output shows the overlap:

gic0: <ARM Generic Interrupt Controller v3.0> iomem 0xffff0000-0x10000ffff, ...... on acpi0

...

ram0: reserving memory region:   100000000-fc0000000
panic: ram_attach: resource 7 failed to attach

[markmi_dsl-only.net]

Looks to me like https://developer.arm.com/documentation/100336/0002/aba1429015078674 has the description of the GICD Distributor registers by offset from the Physical Base Address:

"The following table lists the Distributor registers in base offset order and provides a reference to the register description that is described in either this book or the ARM Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0."

If I read it correctly, GICD_SIZE with the value reported looks reasonable. (But I'm no expert.)

[whu]

Tested the patch in Azure. It fixes the problem.