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[PowerPC] Fix booke64 qemu infinite loop in L2 cache enable
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Authored by bdragon on Jun 11 2020, 2:19 AM.

Details

Summary

Since qemu does not implement the L2 cache, we get stuck forever waiting for a bit to be set when trying to invalidate it.

To prevent that, we should bail out if the L2 cache is missing. One easy way to check this is L2CFG0 == 0 (since L2CSIZE always has at least one bit set in a valid implementation)

(tested on qemu, rb800, and x5000)

Test Plan

Boot on qemu e500 64 bit and hardware.

Diff Detail

Repository
rS FreeBSD src repository
Lint
Automatic diff as part of commit; lint not applicable.
Unit
Automatic diff as part of commit; unit tests not applicable.

Event Timeline

sys/powerpc/booke/machdep_e500.c
99–105 ↗(On Diff #72965)

You could rework it so that instead of bailing early, only do the work if SPR_L2CFG0 != 0; that way you can print out the "L2 cache disabled" below in qemu as well. What do you think?

Reword comment, switch to switching to the end of the function so the message gets printed out as per jhibbits' suggestion.

sys/powerpc/booke/machdep_e500.c
103–111 ↗(On Diff #73067)

I would instead change the condition to be

if (mfspr(SPR_L2CFG0) != 0) {
  ...
}

instead of using the label. At the asm level it's virtually identical, but it reads cleaner in C.

addressing comment by jhibbits

This revision is now accepted and ready to land.Jun 14 2020, 11:55 PM