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dwmmc: Rework the DMA engine
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Authored by manu on Feb 29 2020, 4:57 PM.
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br
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ARM
arm64
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rS358635: dwmmc: Rework the DMA engine
Summary

Each segment can be up to 4096 bytes in chain structure according to the
RK3399 TRM Part 2.
Set the buffers in full ring where the last one point to the first one.
Correctly reports the MMC_IVAR_MAX_DATA.
Use CACHE_LINE_SIZE for bus_dma alignment.

Test Plan

Tested on rock64 (RK3328) and rockpro64 (RK3399)

Diff Detail

Repository
rS FreeBSD src repository - subversion
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Event Timeline

ian added inline comments.
sys/dev/mmc/host/dwmmc.c
122 ↗(On Diff #68992)

The linux driver uses 4096 for this value. Maybe there are other (non-rockchip) implementations that limit it to 4k?

Or, maybe the limit is 8K when des2/des3 both point to buffers, or 4k when DES0_CH is set and des3 points to the chained descriptor?

173 ↗(On Diff #68992)

I think ER should not be set here, it should only be set on the last one in the ring which points back to the start.

sys/dev/mmc/host/dwmmc.c
122 ↗(On Diff #68992)

According to file:///usr/home/manu/Work/Datasheet/SoC/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf DES1 Buffer 1 Size can go up to this value but maybe there is a non rockchip soc that have a different value yes.

manu marked 2 inline comments as done.

Set max size to 8192 for rockchip SoCs.

manu edited the summary of this revision. (Show Details)

Always use 4096 segment size.

manu edited the summary of this revision. (Show Details)

Use CACHE_LINE_SIZE for bus_dma alignment.

@br why 4096 was used for aligment ?
Do you have any platform that strictly require this ?
Could you test if using CACHE_LINE_SIZE works for you ?
Thanks

This revision was not accepted when it landed; it landed in state Needs Review.Mar 4 2020, 8:01 PM
Closed by commit rS358635: dwmmc: Rework the DMA engine (authored by manu). · Explain Why
This revision was automatically updated to reflect the committed changes.