This adds two implementations for each atomic_fcmpset_ and
atomic_cmpset_ short and char functions, selectable at compile time for
the target architecture. By default, it uses a shift-and-mask to
perform atomic updates to sub-components of 32-bit words. However, if
ISA_206_ATOMICS is defined it uses the ll/sc instructions for halfword and
bytes, introduced in PowerISA 2.06. These instructions are supported by
all IBM processors from POWER7 on, as well as the Freescale/NXP e6500
core. Although the e5500 and e500mc both implement PowerISA 2.06 they
do not implement these instructions.
As part of this, clean up the atomic_(f)cmpset_acq and _rel wrappers, by
using macros to reduce code duplication.
ISA_206_ATOMICS requires clang or newer binutils (2.20 or later).