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Add arm_sync_icache() and arm_drain_writebuf() sysarch syscall wrappers.
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Authored by ian on Jul 10 2019, 8:02 PM.

Details

Summary

NetBSD and OpenBSD have libc wrapper functions for the ARM_SYNC_ICACHE and ARM_DRAIN_WRITEBUF operations. This change adds compatible functions to our library. This should make it easier for various upstream sources to support *BSD operating systems with a single variation of cache maintence code in tools like interpreters and JIT compilers.

I consider the argument types passed to arm_sync_icache() to be especially unfortunate, but this is intended to match the other BSDs.

Test Plan

It compiles.

Note: I don't have a lot of experience adding code to libc, please have a look especially at the Symbol.map thing to see if I did it right.

Diff Detail

Repository
rS FreeBSD src repository
Lint
Automatic diff as part of commit; lint not applicable.
Unit
Automatic diff as part of commit; unit tests not applicable.

Event Timeline

ian created this revision.Jul 10 2019, 8:02 PM
kib added a comment.Jul 10 2019, 8:15 PM

Libc symbol versioning chunks look fine.

Are described operations global for all CPUs in the system, or only for the CPU where the caller is executing ? It is not clear from the man pages.

cognet added a subscriber: cognet.Jul 10 2019, 9:37 PM

Obviously at some point I wanted to provide those, and quite obviously as well, I forgot to provide the actual implementation.
That sounds good to me, thanks a lot, Ian !

ian updated this revision to Diff 59621.Jul 10 2019, 11:02 PM

Add some details to the manpage about the barrier and cache operations performed by arm_drain_writebuf().

Clarify in the manpage for arm_sync_icache() that cache maintenance to the level of unification makes the data range coherent amongst all cores. Technically just saying it's a POU operation implies that things are coherent within the Inner Shareable domain of the processor that executes the operation, but that only helps if you're aware of an easy-to-miss sentence in the ARM ARM:

"This architecture is written with an expectation that all processors using the same operating system or hypervisor are in the same Inner Shareable shareability domain."
kib accepted this revision.Jul 11 2019, 11:55 AM
This revision is now accepted and ready to land.Jul 11 2019, 11:55 AM