Align IA32_ARCH_CAP MSR definitions and use with SDM rev. 068.

[kib]

Summary

SDM rev. 068 was released yesterday and it contains the description of the MSR 0x10a IA32_ARCH_CAP. This change adds symbolic definitions for all bits present in the document, and decode them in the CPU identification lines printed on boot.

But also, the document defines SSB_NO as bit 4, while FreeBSD used but 2 to detect the need to work-around Speculative Store Bypass issue. Which one is correct ? I changed code to use the bit from SDM.

Similarly, the document describes bit 3 as an indicator that L1TF issue is not present, in particular, no L1D flush is needed on VMENTRY. We used RDCL_NO to avoid flushing, and again I changed the code to follow new spec from SDM.

In fact my Apollo Lake machine with latest ucode shows this:

IA32_ARCH_CAPS=0x19<RDCL_NO,SKIP_L1DFL_VME,SSB_NO>

[bwidawsk]

I asked for clarification and hopefully, I will have some by the end of the day. My understanding is that RDCL_NO still determines whether or not you need to mitigate L1TF type vulnerabilities.

When SSB_NO is set, RDCL_NO should always also be set (I don't think anything today actually will have SSB_NO). But perhaps that was the source of confusion?

I am not certain why there is a mistake of bit4 vs. bit2. I'll get to the bottom of it.

[bwidawsk]

Can you please identify where the docs say

Similarly, the document describes bit 4 as an indicator that L1TF issue is not present, in particular, no L1D flush is needed on VMENTRY. We used RDCL_NO to avoid flushing, and again I changed the code to follow new spec from SDM.

I see no mention of this bit, otherwise the patch is correct.

[bwidawsk]

Talked with Kostik offline. Patch should say bit 3 instead of 4 for VM entry. Patch itself is correct.