Just allow MSI interrupts to always start at the end of the I/O APIC
pins. Since existing machines already have more than 255 I/O APIC
pins, IRQ 255 is no longer reliably invalid, so just remove the
minimum starting value for MSI.
Details
Details
- Reviewers
kib markj royger - Commits
- rS340488: Axe MINIMUM_MSI_INT.
- boot an amd64 VM under bhyve
- I have not tested Xen.
Diff Detail
Diff Detail
- Repository
- rS FreeBSD src repository - subversion
- Lint
Lint Not Applicable - Unit
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Event Timeline
Comment Actions
It is perhaps debatable if we want this change since it will change the IRQ values users see (and users might be used to >= 256 meaning MSI), and I probably won't MFC it if we do decide we want it in HEAD for those reasons.
sys/x86/xen/pvcpu_enum.c | ||
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202 ↗ | (On Diff #50426) | I believe this matches the intent of the comment. |