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pci_host_generic: remove unneeded ThunderX2 quirk

Authored by jchandra on Oct 22 2018, 11:40 PM.
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The current implementation to write a fixed address to AHCI BARs is not
correct. The PCI address ranges are allocated by firmware and will
change depending on PCI devices present. Using a fixed value here is
not a viable option.

The newer firmware does not have this issue (and the older evaluation
Ax chips with SATA BAR issues are no longer in use), so it is better
to drop this quirk altogether, rather than to fix correctly.

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Is there an easy way to tell which revision silicon we have? I'd like to check the TX2 I have access to.

Is there an easy way to tell which revision silicon we have? I'd like to check the TX2 I have access to.

The MIDR should have the revision info:
Older Broadcom Vulcan (with hardware issues): 0x420f516[12] - it is very unlikely this went out to anyone other than few early evaluation partners
Newer Cavium ThunderX2: 0x431f0af1 (revisions available are 0/1/2 they should be fine)

The older UEFI releases from Cavium has a serious bug - it programmed BAR2 (msix bar) of on board SATA controller with two 32-bit addresses, instead of a single 64-bit address. This has been fixed in newer firmware (getting this requires access to The current releases (7.0/7.1 etc) should have this fix.

You can get firmware version is from SMBIOS tables or from boot log. If you have linux, you can run dmidecode -t 0 and see if the BIOS version is ok.
The support site has firmware update instructions (there are chances that you will end up with a bricked system if you get it wrong).

This revision is now accepted and ready to land.Nov 1 2018, 12:15 PM
This revision was automatically updated to reflect the committed changes.