ums(4): Do not stop USB xfers on FIFO close when evdev is still active
ClosedPublic
Actions

Authored by wulf on May 18 2021, 10:57 PM.

Details

Reviewers

Commits

rG8696dd92ffb7: ums(4): Do not stop USB xfers on FIFO close when evdev is still active
rGa4a738ba7575: ums(4): Do not stop USB xfers on FIFO close when evdev is still active
rG05ab03a31798: ums(4): Do not stop USB xfers on FIFO close when evdev is still active

Summary

This fixes lose of evdev events after moused has been killed.

While here use bitwise operations for UMS_EVDEV_OPENED flag.

Test Plan

Kill moused attached to /dev/ums while a evdev consumer is attached to corresponding input/event device node. Than ensure that evdev events are still produced.

Diff Detail

Repository

rS FreeBSD src repository - subversion

Lint

Lint Passed

Unit

No Test Coverage

Build Status

Buildable 39285
Build 36174: arc lint + arc unit

Event Timeline

wulf created this revision.May 18 2021, 10:57 PM

Herald added subscribers: Contributor Reviews (src), imp. · View Herald TranscriptMay 18 2021, 10:57 PM

wulf requested review of this revision.May 18 2021, 10:57 PM

Harbormaster completed remote builds in B39284: Diff 89456.May 18 2021, 10:57 PM

While here use bitwise operations for UMS_EVDEV_OPENED flag.

Harbormaster completed remote builds in B39285: Diff 89457.May 18 2021, 11:19 PM

wulf edited the summary of this revision. (Show Details)May 18 2021, 11:22 PM

wulf edited the test plan for this revision. (Show Details)

wulf added a reviewer: • hselasky.

• hselasky accepted this revision.May 19 2021, 7:32 AM

This revision is now accepted and ready to land.May 19 2021, 7:32 AM

• hselasky added inline comments.May 19 2021, 7:35 AM

sys/dev/usb/input/ums.c
951	This code must be under: #ifdef XXX
968	This code must be under #ifdef XXX

wulf marked 2 inline comments as done.May 19 2021, 7:47 AM

wulf added inline comments.

sys/dev/usb/input/ums.c
951	This code must be under: #ifdef XXX It already is. See line 943

Good!

Closed by commit rG05ab03a31798: ums(4): Do not stop USB xfers on FIFO close when evdev is still active (authored by wulf). · Explain WhyMay 23 2021, 10:44 PM

This revision was automatically updated to reflect the committed changes.

wulf marked an inline comment as done.

wulf added a commit: rG05ab03a31798: ums(4): Do not stop USB xfers on FIFO close when evdev is still active.

wulf added a commit: rGa4a738ba7575: ums(4): Do not stop USB xfers on FIFO close when evdev is still active.Jun 13 2021, 10:03 PM

wulf added a commit: rG8696dd92ffb7: ums(4): Do not stop USB xfers on FIFO close when evdev is still active.Jun 13 2021, 10:08 PM

Revision Contents
Changeset List

Path

Size

sys/

dev/

usb/

input/

ums.c

13 lines

Diff 89457

View Options

sys/dev/usb/input/ums.c

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
#define PCIE_REG_MASK 0xFFF		#define PCIE_REG_MASK 0xFFF

#define PCIE_ADDR_OFFSET(bus, slot, func, reg) \		#define PCIE_ADDR_OFFSET(bus, slot, func, reg) \
((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) \| \		((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) \| \
(((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) \| \		(((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) \| \
(((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) \| \		(((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) \| \
((reg) & PCIE_REG_MASK))		((reg) & PCIE_REG_MASK))

		typedef void (*pci_host_generic_quirk_function)(device_t);

		struct pci_host_generic_quirk_entry {
		int impl;
		int part;
		int var;
		int rev;
		pci_host_generic_quirk_function func;
		};

		struct pci_host_generic_block_entry {
		int impl;
		int part;
		int var;
		int rev;
		int bus;
		int slot;
		};

/* Forward prototypes */		/* Forward prototypes */

static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot,		static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, int bytes);		u_int func, u_int reg, int bytes);
static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot,		static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, uint32_t val, int bytes);		u_int func, u_int reg, uint32_t val, int bytes);
static int generic_pcie_maxslots(device_t dev);		static int generic_pcie_maxslots(device_t dev);
static int generic_pcie_read_ivar(device_t dev, device_t child, int index,		static int generic_pcie_read_ivar(device_t dev, device_t child, int index,
uintptr_t *result);		uintptr_t *result);
static int generic_pcie_write_ivar(device_t dev, device_t child, int index,		static int generic_pcie_write_ivar(device_t dev, device_t child, int index,
uintptr_t value);		uintptr_t value);
		static void pci_host_generic_apply_quirks(device_t);
		static void thunderx2_ahci_bar_quirk(device_t);

		struct pci_host_generic_quirk_entry pci_host_generic_quirks[] =
		{
		{CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, thunderx2_ahci_bar_quirk},
		{0, 0, 0, 0, NULL}
		};

		struct pci_host_generic_block_entry pci_host_generic_blocked[] =
		{
		/* ThunderX2 AHCI on second socket */
		{CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, 0x80, 0x10},
		{0, 0, 0, 0, 0, 0}
		};
		andrewUnsubmitted Not Done Inline Actions Why is this needed? andrew: Why is this needed?
		pdk_semihalf.comAuthorUnsubmitted Not Done Inline Actions Second socket have SATA controller on chip. It is not exposed on board, and have bad adresses (like SATA on first socket). Instead of fixing addresses we block it. pdk_semihalf.com: Second socket have SATA controller on chip. It is not exposed on board, and have bad adresses…

int		int
pci_host_generic_core_attach(device_t dev)		pci_host_generic_core_attach(device_t dev)
{		{
struct generic_pcie_core_softc *sc;		struct generic_pcie_core_softc *sc;
int error;		int error;
int rid;		int rid;

sc = device_get_softc(dev);		sc = device_get_softc(dev);
Show All 37 Lines	pci_host_generic_core_attach(device_t dev)
}		}

error = rman_init(&sc->io_rman);		error = rman_init(&sc->io_rman);
if (error) {		if (error) {
device_printf(dev, "rman_init() failed. error = %d\n", error);		device_printf(dev, "rman_init() failed. error = %d\n", error);
return (error);		return (error);
}		}

		pci_host_generic_apply_quirks(dev);

return (0);		return (0);
}		}

		static void
		pci_host_generic_apply_quirks(device_t dev)
		{
		struct pci_host_generic_quirk_entry *quirk;

		quirk = pci_host_generic_quirks;
		while (1) {
		if (quirk->impl == 0)
		break;

		if (CPU_MATCH(CPU_IMPL_MASK \| CPU_PART_MASK,
		quirk->impl, quirk->part, quirk->var, quirk->rev) &&
		quirk->func != NULL)
		quirk->func(dev);

		quirk++;
		}
		}

static uint32_t		static uint32_t
generic_pcie_read_config(device_t dev, u_int bus, u_int slot,		generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, int bytes)		u_int func, u_int reg, int bytes)
{		{
struct generic_pcie_core_softc *sc;		struct generic_pcie_core_softc *sc;
bus_space_handle_t h;		bus_space_handle_t h;
bus_space_tag_t t;		bus_space_tag_t t;
uint64_t offset;		uint64_t offset;
uint32_t data;		uint32_t data;
		struct pci_host_generic_block_entry *block;

if ((bus > PCI_BUSMAX) \|\| (slot > PCI_SLOTMAX) \|\|		if ((bus > PCI_BUSMAX) \|\| (slot > PCI_SLOTMAX) \|\|
(func > PCI_FUNCMAX) \|\| (reg > PCIE_REGMAX))		(func > PCI_FUNCMAX) \|\| (reg > PCIE_REGMAX))
return (~0U);		return (~0U);

		block = pci_host_generic_blocked;
		while (1) {
		if (block->impl == 0)
		break;

		if (CPU_MATCH(CPU_IMPL_MASK \| CPU_PART_MASK,
		block->impl, block->part, block->var, block->rev) &&
		block->bus == bus && block->slot == slot)
		return (~0);

		block++;
		}

sc = device_get_softc(dev);		sc = device_get_softc(dev);

offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);		offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);
t = sc->bst;		t = sc->bst;
h = sc->bsh;		h = sc->bsh;

switch (bytes) {		switch (bytes) {
case 1:		case 1:
▲ Show 20 Lines • Show All 224 Lines • ▼ Show 20 Lines	static device_method_t generic_pcie_methods[] = {
DEVMETHOD(pcib_read_config, generic_pcie_read_config),		DEVMETHOD(pcib_read_config, generic_pcie_read_config),
DEVMETHOD(pcib_write_config, generic_pcie_write_config),		DEVMETHOD(pcib_write_config, generic_pcie_write_config),

DEVMETHOD_END		DEVMETHOD_END
};		};

DEFINE_CLASS_0(pcib, generic_pcie_core_driver,		DEFINE_CLASS_0(pcib, generic_pcie_core_driver,
generic_pcie_methods, sizeof(struct generic_pcie_core_softc));		generic_pcie_methods, sizeof(struct generic_pcie_core_softc));

		static void thunderx2_ahci_bar_quirk(device_t dev)
		{

		/*
		* XXX:
		* On ThunderX2, AHCI BAR2 address is wrong. It needs to precisely
		* match the one described in datasheet. Fixup it unconditionally.
		andrewUnsubmitted Not Done Inline Actions Is there an erratum for this? andrew: Is there an erratum for this?
		pdk_semihalf.comAuthorUnsubmitted Not Done Inline Actions There is no erratum. Without this quirk kernel is trying to access bad address. pdk_semihalf.com: There is no erratum. Without this quirk kernel is trying to access bad address.
		andrewUnsubmitted Not Done Inline Actions Why is the kernel trying to access a bad address? andrew: Why is the kernel trying to access a bad address?
		pdk_semihalf.comAuthorUnsubmitted Not Done Inline Actions Kernel is trying to attach ahci. Look at log (without quirk of course) below it contains aforementioned bad address: ahci0: <AHCI SATA controller> mem 0x41d4100041d30000-0x41d4100041d3ffff,0x41d20000-0x41d2ffff at device 16.0 on pci0 PDK: virtual=0xffff000165388000 size=65536 pa=41d20000 PDK: virtual=0xffff000165398000 size=65536 pa=41d4100041d30000 ahci0: PDK: msix_table_bar: 24 ahci0: PDK: msix_table_res: 0xfffffd0001e25180 ahci0: attempting to allocate 4 MSI-X vectors (4 supported) ahci0: using IRQs 11-14 for MSI-X panic: vm_fault_hold: fault on nofault entry, addr: 0xffff000165398000 pdk_semihalf.com: Kernel is trying to attach ahci. Look at log (without quirk of course) below it contains…
		*/
		if (device_get_unit(dev) == 0) {
		device_printf(dev, "running AHCI BAR fixup\n");
		PCIB_WRITE_CONFIG(dev, 0, 16, 0, 0x18, 0x01440000, 4);
		PCIB_WRITE_CONFIG(dev, 0, 16, 0, 0x1c, 0x40, 4);
		PCIB_WRITE_CONFIG(dev, 0, 16, 1, 0x18, 0x01450000, 4);
		PCIB_WRITE_CONFIG(dev, 0, 16, 1, 0x1c, 0x40, 4);
		}
		}
		andrewUnsubmitted Not Done Inline Actions Shouldn't you be getting this from the ACPI mcfg table? andrew: Shouldn't you be getting this from the ACPI mcfg table?
		pdk_semihalf.comAuthorUnsubmitted Not Done Inline Actions Yes, I should get this from MCFG, but it doesn't provide information about pci on second socket. Furthermore segment passed to acpi_enable_pcie is 0 in both cases. pdk_semihalf.com: Yes, I should get this from MCFG, but it doesn't provide information about pci on second socket.
		andrewUnsubmitted Not Done Inline Actions Will this always be unit 16, or would it be better to look at other information to detect when it's an ecam device. andrew: Will this always be unit 16, or would it be better to look at other information to detect when…
		pdk_semihalf.comAuthorUnsubmitted Not Done Inline Actions It will be always unit 16. I've checked it once again and I have an idea. I will use _BBN to get ecam number. I'll update patches today so stay tuned. pdk_semihalf.com: It will be always unit 16. I've checked it once again and I have an idea. I will use _BBN to…

ums(4): Do not stop USB xfers on FIFO close when evdev is still activeClosedPublicActions