riscv: Assert that SUM is not set in SSTATUS for exceptions.
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Authored by jhb on Apr 14 2021, 4:46 PM.

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imp

riscv

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mhorne
jrtc27

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rG05504819e39d: riscv: Assert that SUM is not set in SSTATUS for exceptions.
rG6a3a6fe34bf3: riscv: Assert that SUM is not set in SSTATUS for exceptions.

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rS FreeBSD src repository - subversion

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Buildable 38577
Build 35466: arc lint + arc unit

Event Timeline

jhb created this revision.Apr 14 2021, 4:46 PM

Herald added a subscriber: imp. · View Herald TranscriptApr 14 2021, 4:46 PM

jhb requested review of this revision.Apr 14 2021, 4:46 PM

Harbormaster completed remote builds in B38577: Diff 87447.Apr 14 2021, 4:46 PM

jhb added a parent revision: D29763: riscv: Clear SUM in SSTATUS for supervisor mode exceptions..Apr 14 2021, 4:46 PM

mhorne accepted this revision.Apr 21 2021, 4:47 PM

This revision is now accepted and ready to land.Apr 21 2021, 4:47 PM

Closed by commit rG6a3a6fe34bf3: riscv: Assert that SUM is not set in SSTATUS for exceptions. (authored by jhb). · Explain WhyApr 21 2021, 8:58 PM

This revision was automatically updated to reflect the committed changes.

jhb added a commit: rG6a3a6fe34bf3: riscv: Assert that SUM is not set in SSTATUS for exceptions..

jhb added a commit: rG05504819e39d: riscv: Assert that SUM is not set in SSTATUS for exceptions..Nov 23 2021, 11:49 PM

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sys/

riscv/

trap.c

6 lines

Diff 87447

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riscv: Assert that SUM is not set in SSTATUS for exceptions.ClosedPublicActions