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Differential D27396

Add IRQ resource to SPIBUS
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Authored by oskar.holmlund_ohdata.se on Nov 27 2020, 5:30 PM.
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mmel
manu
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ARM
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rS368725: Add IRQ resource to SPIBUS
Summary

Add capability to SPIBUS to have child device with IRQ.
For example many ADC chip have a dedicated pin to signal "data ready" and the host can just wait for a interrupt to go out and read the result.

It is the same code as in R282674 and R282702 for IICBUS by Michal Meloun

Diff Detail

Repository
rS FreeBSD src repository - subversion
Lint
Lint Not Applicable
Unit
Tests Not Applicable

Revision Contents
Changeset List

PathSize
head/
sys/
dev/
spibus/
14 lines
29 lines
1 line

Diff 80837

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head/sys/dev/spibus/ofw_spibus.c

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
MODULE_DEPEND(nvme, cam, 1, 1, 1); MODULE_DEPEND(nvme, cam, 1, 1, 1);
static struct _pcsid static struct _pcsid
{ {
uint32_t devid; uint32_t devid;
int match_subdevice; int match_subdevice;
uint16_t subdevice; uint16_t subdevice;
const char *desc; const char *desc;
uint32_t quirks;
} pci_ids[] = { } pci_ids[] = {
{ 0x01118086, 0, 0, "NVMe Controller" }, { 0x01118086, 0, 0, "NVMe Controller" },
{ IDT32_PCI_ID, 0, 0, "IDT NVMe Controller (32 channel)" }, { IDT32_PCI_ID, 0, 0, "IDT NVMe Controller (32 channel)" },
{ IDT8_PCI_ID, 0, 0, "IDT NVMe Controller (8 channel)" }, { IDT8_PCI_ID, 0, 0, "IDT NVMe Controller (8 channel)" },
{ 0x09538086, 1, 0x3702, "DC P3700 SSD" }, { 0x09538086, 1, 0x3702, "DC P3700 SSD" },
{ 0x09538086, 1, 0x3703, "DC P3700 SSD [2.5\" SFF]" }, { 0x09538086, 1, 0x3703, "DC P3700 SSD [2.5\" SFF]" },
{ 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" }, { 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" },
{ 0x09538086, 1, 0x3705, "DC P3500 SSD [2.5\" SFF]" }, { 0x09538086, 1, 0x3705, "DC P3500 SSD [2.5\" SFF]" },
{ 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" }, { 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" },
{ 0x09538086, 1, 0x370a, "DC P3600 SSD [2.5\" SFF]" }, { 0x09538086, 1, 0x370a, "DC P3600 SSD [2.5\" SFF]" },
{ 0x00031c58, 0, 0, "HGST SN100", QUIRK_DELAY_B4_CHK_RDY },
{ 0x00231c58, 0, 0, "WDC SN200", QUIRK_DELAY_B4_CHK_RDY },
{ 0x05401c5f, 0, 0, "Memblaze Pblaze4", QUIRK_DELAY_B4_CHK_RDY },
{ 0xa821a821, 0, 0, "Samsung PM1725", QUIRK_DELAY_B4_CHK_RDY },
chuckUnsubmitted
Not Done
Inline Actions

Should the device ID be 0xa821144d?

chuck: Should the device ID be `0xa821144d`?
impAuthorUnsubmitted
Not Done
Inline Actions

yup

imp: yup
{ 0xa821a822, 0, 0, "Samsung PM1725a", QUIRK_DELAY_B4_CHK_RDY },
chuckUnsubmitted
Not Done
Inline Actions

Should the device ID be 0xa822144d?

chuck: Should the device ID be `0xa822144d`?
impAuthorUnsubmitted
Not Done
Inline Actions

yup.

imp: yup.
{ 0x00000000, 0, 0, NULL } { 0x00000000, 0, 0, NULL }
}; };
static int static int
nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep) nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep)
{ {
if (devid != ep->devid) if (devid != ep->devid)
return 0; return 0;
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines printf("cdw0:%08x sqhd:%04x sqid:%04x "
cpl->status.m, cpl->status.dnr); cpl->status.m, cpl->status.dnr);
} }
static int static int
nvme_attach(device_t dev) nvme_attach(device_t dev)
{ {
struct nvme_controller *ctrlr = DEVICE2SOFTC(dev); struct nvme_controller *ctrlr = DEVICE2SOFTC(dev);
int status; int status;
struct _pcsid *ep;
uint32_t devid;
uint16_t subdevice;
devid = pci_get_devid(dev);
subdevice = pci_get_subdevice(dev);
ep = pci_ids;
while (ep->devid) {
if (nvme_match(devid, subdevice, ep))
break;
++ep;
}
ctrlr->quirks = ep->quirks;
status = nvme_ctrlr_construct(ctrlr, dev); status = nvme_ctrlr_construct(ctrlr, dev);
if (status != 0) { if (status != 0) {
nvme_ctrlr_destruct(ctrlr, dev); nvme_ctrlr_destruct(ctrlr, dev);
return (status); return (status);
} }
▲ Show 20 Lines • Show All 205 Lines • Show Last 20 Lines
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head/sys/dev/spibus/spibus.c

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
MODULE_DEPEND(nvme, cam, 1, 1, 1); MODULE_DEPEND(nvme, cam, 1, 1, 1);
static struct _pcsid static struct _pcsid
{ {
uint32_t devid; uint32_t devid;
int match_subdevice; int match_subdevice;
uint16_t subdevice; uint16_t subdevice;
const char *desc; const char *desc;
uint32_t quirks;
} pci_ids[] = { } pci_ids[] = {
{ 0x01118086, 0, 0, "NVMe Controller" }, { 0x01118086, 0, 0, "NVMe Controller" },
{ IDT32_PCI_ID, 0, 0, "IDT NVMe Controller (32 channel)" }, { IDT32_PCI_ID, 0, 0, "IDT NVMe Controller (32 channel)" },
{ IDT8_PCI_ID, 0, 0, "IDT NVMe Controller (8 channel)" }, { IDT8_PCI_ID, 0, 0, "IDT NVMe Controller (8 channel)" },
{ 0x09538086, 1, 0x3702, "DC P3700 SSD" }, { 0x09538086, 1, 0x3702, "DC P3700 SSD" },
{ 0x09538086, 1, 0x3703, "DC P3700 SSD [2.5\" SFF]" }, { 0x09538086, 1, 0x3703, "DC P3700 SSD [2.5\" SFF]" },
{ 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" }, { 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" },
{ 0x09538086, 1, 0x3705, "DC P3500 SSD [2.5\" SFF]" }, { 0x09538086, 1, 0x3705, "DC P3500 SSD [2.5\" SFF]" },
{ 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" }, { 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" },
{ 0x09538086, 1, 0x370a, "DC P3600 SSD [2.5\" SFF]" }, { 0x09538086, 1, 0x370a, "DC P3600 SSD [2.5\" SFF]" },
{ 0x00031c58, 0, 0, "HGST SN100", QUIRK_DELAY_B4_CHK_RDY },
{ 0x00231c58, 0, 0, "WDC SN200", QUIRK_DELAY_B4_CHK_RDY },
{ 0x05401c5f, 0, 0, "Memblaze Pblaze4", QUIRK_DELAY_B4_CHK_RDY },
{ 0xa821a821, 0, 0, "Samsung PM1725", QUIRK_DELAY_B4_CHK_RDY },
chuckUnsubmitted
Not Done
Inline Actions

Should the device ID be 0xa821144d?

chuck: Should the device ID be `0xa821144d`?
impAuthorUnsubmitted
Not Done
Inline Actions

yup

imp: yup
{ 0xa821a822, 0, 0, "Samsung PM1725a", QUIRK_DELAY_B4_CHK_RDY },
chuckUnsubmitted
Not Done
Inline Actions

Should the device ID be 0xa822144d?

chuck: Should the device ID be `0xa822144d`?
impAuthorUnsubmitted
Not Done
Inline Actions

yup.

imp: yup.
{ 0x00000000, 0, 0, NULL } { 0x00000000, 0, 0, NULL }
}; };
static int static int
nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep) nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep)
{ {
if (devid != ep->devid) if (devid != ep->devid)
return 0; return 0;
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines printf("cdw0:%08x sqhd:%04x sqid:%04x "
cpl->status.m, cpl->status.dnr); cpl->status.m, cpl->status.dnr);
} }
static int static int
nvme_attach(device_t dev) nvme_attach(device_t dev)
{ {
struct nvme_controller *ctrlr = DEVICE2SOFTC(dev); struct nvme_controller *ctrlr = DEVICE2SOFTC(dev);
int status; int status;
struct _pcsid *ep;
uint32_t devid;
uint16_t subdevice;
devid = pci_get_devid(dev);
subdevice = pci_get_subdevice(dev);
ep = pci_ids;
while (ep->devid) {
if (nvme_match(devid, subdevice, ep))
break;
++ep;
}
ctrlr->quirks = ep->quirks;
status = nvme_ctrlr_construct(ctrlr, dev); status = nvme_ctrlr_construct(ctrlr, dev);
if (status != 0) { if (status != 0) {
nvme_ctrlr_destruct(ctrlr, dev); nvme_ctrlr_destruct(ctrlr, dev);
return (status); return (status);
} }
▲ Show 20 Lines • Show All 205 Lines • Show Last 20 Lines
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head/sys/dev/spibus/spibusvar.h

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
MODULE_DEPEND(nvme, cam, 1, 1, 1); MODULE_DEPEND(nvme, cam, 1, 1, 1);
static struct _pcsid static struct _pcsid
{ {
uint32_t devid; uint32_t devid;
int match_subdevice; int match_subdevice;
uint16_t subdevice; uint16_t subdevice;
const char *desc; const char *desc;
uint32_t quirks;
} pci_ids[] = { } pci_ids[] = {
{ 0x01118086, 0, 0, "NVMe Controller" }, { 0x01118086, 0, 0, "NVMe Controller" },
{ IDT32_PCI_ID, 0, 0, "IDT NVMe Controller (32 channel)" }, { IDT32_PCI_ID, 0, 0, "IDT NVMe Controller (32 channel)" },
{ IDT8_PCI_ID, 0, 0, "IDT NVMe Controller (8 channel)" }, { IDT8_PCI_ID, 0, 0, "IDT NVMe Controller (8 channel)" },
{ 0x09538086, 1, 0x3702, "DC P3700 SSD" }, { 0x09538086, 1, 0x3702, "DC P3700 SSD" },
{ 0x09538086, 1, 0x3703, "DC P3700 SSD [2.5\" SFF]" }, { 0x09538086, 1, 0x3703, "DC P3700 SSD [2.5\" SFF]" },
{ 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" }, { 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" },
{ 0x09538086, 1, 0x3705, "DC P3500 SSD [2.5\" SFF]" }, { 0x09538086, 1, 0x3705, "DC P3500 SSD [2.5\" SFF]" },
{ 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" }, { 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" },
{ 0x09538086, 1, 0x370a, "DC P3600 SSD [2.5\" SFF]" }, { 0x09538086, 1, 0x370a, "DC P3600 SSD [2.5\" SFF]" },
{ 0x00031c58, 0, 0, "HGST SN100", QUIRK_DELAY_B4_CHK_RDY },
{ 0x00231c58, 0, 0, "WDC SN200", QUIRK_DELAY_B4_CHK_RDY },
{ 0x05401c5f, 0, 0, "Memblaze Pblaze4", QUIRK_DELAY_B4_CHK_RDY },
{ 0xa821a821, 0, 0, "Samsung PM1725", QUIRK_DELAY_B4_CHK_RDY },
chuckUnsubmitted
Not Done
Inline Actions

Should the device ID be 0xa821144d?

chuck: Should the device ID be `0xa821144d`?
impAuthorUnsubmitted
Not Done
Inline Actions

yup

imp: yup
{ 0xa821a822, 0, 0, "Samsung PM1725a", QUIRK_DELAY_B4_CHK_RDY },
chuckUnsubmitted
Not Done
Inline Actions

Should the device ID be 0xa822144d?

chuck: Should the device ID be `0xa822144d`?
impAuthorUnsubmitted
Not Done
Inline Actions

yup.

imp: yup.
{ 0x00000000, 0, 0, NULL } { 0x00000000, 0, 0, NULL }
}; };
static int static int
nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep) nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep)
{ {
if (devid != ep->devid) if (devid != ep->devid)
return 0; return 0;
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines printf("cdw0:%08x sqhd:%04x sqid:%04x "
cpl->status.m, cpl->status.dnr); cpl->status.m, cpl->status.dnr);
} }
static int static int
nvme_attach(device_t dev) nvme_attach(device_t dev)
{ {
struct nvme_controller *ctrlr = DEVICE2SOFTC(dev); struct nvme_controller *ctrlr = DEVICE2SOFTC(dev);
int status; int status;
struct _pcsid *ep;
uint32_t devid;
uint16_t subdevice;
devid = pci_get_devid(dev);
subdevice = pci_get_subdevice(dev);
ep = pci_ids;
while (ep->devid) {
if (nvme_match(devid, subdevice, ep))
break;
++ep;
}
ctrlr->quirks = ep->quirks;
status = nvme_ctrlr_construct(ctrlr, dev); status = nvme_ctrlr_construct(ctrlr, dev);
if (status != 0) { if (status != 0) {
nvme_ctrlr_destruct(ctrlr, dev); nvme_ctrlr_destruct(ctrlr, dev);
return (status); return (status);
} }
▲ Show 20 Lines • Show All 205 Lines • Show Last 20 Lines