prci: register the DDR and GEMGX PLLs
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Authored by mhorne on Jan 28 2020, 7:58 PM.

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Reviewers

kp
philip

Group Reviewers

riscv

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rS357369: prci: register the DDR and GEMGX PLLs

Summary

The PRCI module exports three PLLs. Currently only the coreclk/corepll
is registered, so add the logic to register the DDR (memory) and GEMGX
(ethernet) clocks as well.

See also: Chapter 7 of the FU540 manual.

Test Plan

I have booted this with the qemu "sifive_u" platform, and dmesg shows
that the clocks are registered. I would prefer this set of changes be
tested on a real SiFive Unleashed though.

Sysctl output showing the new PLLs:

dev.fu540prci.0.clocks: coreclk ddrclk gemgxclk tlclk 
...
hw.clock.gemgxclk.enable_cnt: 0
hw.clock.gemgxclk.childrens: 
hw.clock.gemgxclk.parents: hfclk rtcclk 
hw.clock.gemgxclk.parent: hfclk
hw.clock.gemgxclk.frequency: 0
hw.clock.ddrclk.enable_cnt: 0
hw.clock.ddrclk.childrens: 
hw.clock.ddrclk.parents: hfclk rtcclk 
hw.clock.ddrclk.parent: hfclk
hw.clock.ddrclk.frequency: 0

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Build Status

Buildable 28997
Build 26971: arc lint + arc unit

Event Timeline

mhorne created this revision.Jan 28 2020, 7:58 PM

Harbormaster completed remote builds in B28997: Diff 67431.Jan 28 2020, 7:58 PM

mhorne edited the test plan for this revision. (Show Details)Jan 28 2020, 8:05 PM

At first glance this looks good.
I have a SiFive FU540 I can test with tomorrow.

I only implemented the core clock because it feeds the SPI / UART / I2C clocks. The DDR and gigabit ethernet clocks were not relevant.

mhorne edited the summary of this revision. (Show Details)Jan 28 2020, 8:15 PM

mhorne edited the test plan for this revision. (Show Details)

In D23404#513349, @kp wrote:

At first glance this looks good.
I have a SiFive FU540 I can test with tomorrow.

I only implemented the core clock because it feeds the SPI / UART / I2C clocks. The DDR and gigabit ethernet clocks were not relevant.

Thanks. They will still be unused/irrelevant at present, but my thinking is that it is useful to have so we can eventually set the cgem's reference clock.

Fix DDR and GEMGX clock IDs

Harbormaster completed remote builds in B29004: Diff 67438.Jan 28 2020, 10:24 PM

In D23404#513373, @mhorne wrote:

In D23404#513349, @kp wrote:

At first glance this looks good.
I have a SiFive FU540 I can test with tomorrow.

I only implemented the core clock because it feeds the SPI / UART / I2C clocks. The DDR and gigabit ethernet clocks were not relevant.

Thanks. They will still be unused/irrelevant at present, but my thinking is that it is useful to have so we can eventually set the cgem's reference clock.

Having looked at D23406 it makes even more sense why we'd want to add these. I'm making a build with all of your patches right now so I can test on my board. I don't expect any issues, they all look good.