prci: register the DDR and GEMGX PLLs

[mhorne]

Summary

The PRCI module exports three PLLs. Currently only the coreclk/corepll
is registered, so add the logic to register the DDR (memory) and GEMGX
(ethernet) clocks as well.

See also: Chapter 7 of the FU540 manual.

Test Plan

I have booted this with the qemu "sifive_u" platform, and dmesg shows
that the clocks are registered. I would prefer this set of changes be
tested on a real SiFive Unleashed though.

Sysctl output showing the new PLLs:

dev.fu540prci.0.clocks: coreclk ddrclk gemgxclk tlclk 
...
hw.clock.gemgxclk.enable_cnt: 0
hw.clock.gemgxclk.childrens: 
hw.clock.gemgxclk.parents: hfclk rtcclk 
hw.clock.gemgxclk.parent: hfclk
hw.clock.gemgxclk.frequency: 0
hw.clock.ddrclk.enable_cnt: 0
hw.clock.ddrclk.childrens: 
hw.clock.ddrclk.parents: hfclk rtcclk 
hw.clock.ddrclk.parent: hfclk
hw.clock.ddrclk.frequency: 0

[kp]

At first glance this looks good.
I have a SiFive FU540 I can test with tomorrow.

I only implemented the core clock because it feeds the SPI / UART / I2C clocks. The DDR and gigabit ethernet clocks were not relevant.

[mhorne]

In D23404#513349, @kp wrote:

At first glance this looks good.
I have a SiFive FU540 I can test with tomorrow.

I only implemented the core clock because it feeds the SPI / UART / I2C clocks. The DDR and gigabit ethernet clocks were not relevant.

Thanks. They will still be unused/irrelevant at present, but my thinking is that it is useful to have so we can eventually set the cgem's reference clock.

[mhorne]

Fix DDR and GEMGX clock IDs

[kp]

In D23404#513373, @mhorne wrote:

In D23404#513349, @kp wrote:

At first glance this looks good.
I have a SiFive FU540 I can test with tomorrow.

I only implemented the core clock because it feeds the SPI / UART / I2C clocks. The DDR and gigabit ethernet clocks were not relevant.

Thanks. They will still be unused/irrelevant at present, but my thinking is that it is useful to have so we can eventually set the cgem's reference clock.

Having looked at D23406 it makes even more sense why we'd want to add these. I'm making a build with all of your patches right now so I can test on my board. I don't expect any issues, they all look good.

[kp]

This patch series is happy on my SiFive FU540 board, and I'm happy with the patches.