I think the changes in this file could be committed independently

sounds reasonable, thanks!

This file could be split out and committed as is (although it won't work as we don't have ptrace support).

what is this change for?

This should be sorted, aarch64 should be before amd64.

This doesn't disable interrupts, only sets them to be disabled when returning from an exception. To disable them you need the daif register.

See dtrace_interrupt_disable above

Why not ldrb w0, [x0]? Then there is no need for the mov.

This is wrong, it loads & stores data in 4-byte chunks, but then increments the address by 1. I expect you were intendign to use ldrb and strb here.

You will need tow versions of this as sizeof(uint32_t) != sizeof(void *)

This coment is incorrect, the 5th parameter is in x4.

so in order to emulate 'store pair' instruction we have to reserve space (minimum required 96 bytes, I set 128).

in case frame->tf_sp not changed during trap (say dtrace turned off), we have to skip 128 bytes reserved space. If frame->tf_sp changed, it will be used as new SP.

I've reworked the code to simplify this. frame->tf_sp is the value of sp when entering the exception handler, you can adjust it as needed in save_registers after the mov x18, sp instruction.

thanks! - it is much easier now

What is 0x3 for? If it's to check an alignment we should add a macro for this.

Is this just used in userland? We should allocate a unique value for it.

Why 128?

This looks wrong for the 32-bit store, it will write to sp and sp + 8 bytes, where it should write to sp and sp + 4 bytes.

This has the same issue as above with the 32-bit instructions. do we need them? I would only expect to see them used when using the 32-bit ABI in userland.

We need #define INSN_SIZE 4 in a header for use here.

Why are you searching for ldp and not ret?

ok thanks - I changed to daifset, daifclr

ok,thanks. Lets leave STP/LDP 64bit version only

ok leave 64-bit versions only

right

ok I eliminated this number

header added

comment removed

splitted for two versions

ok lets try with ret instead of ldp. Looking on trace I see it does not really matters

What do we need to do here (for arm/mips in general, not just aarch64)?

and what do we need to do here?

Yes, I'd like to see this committed as is. The aarch64 #ifs should be resorted to be first though to keep alpha order.

See https://gcc.gnu.org/ml/gcc-patches/2013-11/msg02228.html

This should be in alphabetical order, aarch64 should be before arm.

And this

And this

This should be sorted, it was missed when arm was added, but that shouldn't mean we do the same with AArch64.

Alphabetical

Alphabetical

Alphabetical

Can you use a different brk value? It might also pay to document them on the wiki.

You should also check the breakpoint instruction has the correct value so we don't hit the ddb brk.

Why not replace these two instructions with cbnz?

And here

This should be a unique value in the EL1 range.

Does this function exist on arm64?

This list should be checked in some central location.

There is no branch delay slot on arm. It's also a bug in the 32-bit dtrace code.

POPM? Shouldn't it be named DTRACE_INVOP_RET?

So I set 0x14 for libproc and 0x40d for dtrace

I have set 20 as BRK value. See BREAKPOINT_INSTR define

Ok let it be 0x40d

not sure

what you mean?

right, thanks