basic stuff implemented
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| sys/arm64/arm64/db_trace.c | ||
|---|---|---|
| 77 ↗ | (On Diff #5965) | I think the changes in this file could be committed independently |
| sys/arm64/arm64/db_trace.c | ||
|---|---|---|
| 77 ↗ | (On Diff #5965) | sounds reasonable, thanks! |
| lib/libproc/proc_regs.c | ||
|---|---|---|
| 62 ↗ | (On Diff #5965) | This file could be split out and committed as is (although it won't work as we don't have ptrace support). |
| sys/arm64/arm64/exception.S | ||
| 72–83 ↗ | (On Diff #5965) | what is this change for? |
| sys/cddl/contrib/opensolaris/uts/common/dtrace/dtrace.c | ||
| 11887 ↗ | (On Diff #5965) | This should be sorted, aarch64 should be before amd64. |
| sys/cddl/dev/dtrace/aarch64/dtrace_asm.S | ||
| 58–61 ↗ | (On Diff #5965) | This doesn't disable interrupts, only sets them to be disabled when returning from an exception. To disable them you need the daif register. |
| 69–73 ↗ | (On Diff #5965) | See dtrace_interrupt_disable above |
| 81 ↗ | (On Diff #5965) | Why not ldrb w0, [x0]? Then there is no need for the mov. |
| 123–126 ↗ | (On Diff #5965) | This is wrong, it loads & stores data in 4-byte chunks, but then increments the address by 1. I expect you were intendign to use ldrb and strb here. |
| 165–166 ↗ | (On Diff #5965) | You will need tow versions of this as sizeof(uint32_t) != sizeof(void *) |
| sys/cddl/dev/fbt/aarch64/fbt_isa.c | ||
| 61 ↗ | (On Diff #5965) | This coment is incorrect, the 5th parameter is in x4. |
| sys/arm64/arm64/exception.S | ||
|---|---|---|
| 72–83 ↗ | (On Diff #5987) | so in order to emulate 'store pair' instruction we have to reserve space (minimum required 96 bytes, I set 128). in case frame->tf_sp not changed during trap (say dtrace turned off), we have to skip 128 bytes reserved space. If frame->tf_sp changed, it will be used as new SP. |
| sys/arm64/arm64/exception.S | ||
|---|---|---|
| 72–83 ↗ | (On Diff #5987) | I've reworked the code to simplify this. frame->tf_sp is the value of sp when entering the exception handler, you can adjust it as needed in save_registers after the mov x18, sp instruction. |
| sys/arm64/arm64/exception.S | ||
|---|---|---|
| 71–82 ↗ | (On Diff #6010) | thanks! - it is much easier now |
| cddl/contrib/opensolaris/lib/libdtrace/aarch64/dt_isadep.c | ||
|---|---|---|
| 82 ↗ | (On Diff #6010) | What is 0x3 for? If it's to check an alignment we should add a macro for this. |
| lib/libproc/proc_bkpt.c | ||
| 58 ↗ | (On Diff #6010) | Is this just used in userland? We should allocate a unique value for it. |
| sys/cddl/dev/dtrace/aarch64/dtrace_subr.c | ||
| 259 ↗ | (On Diff #6010) | Why 128? |
| 260–261 ↗ | (On Diff #6010) | This looks wrong for the 32-bit store, it will write to sp and sp + 8 bytes, where it should write to sp and sp + 4 bytes. |
| 265–266 ↗ | (On Diff #6010) | This has the same issue as above with the 32-bit instructions. do we need them? I would only expect to see them used when using the 32-bit ABI in userland. |
| 275 ↗ | (On Diff #6010) | We need #define INSN_SIZE 4 in a header for use here. |
| sys/cddl/dev/fbt/aarch64/fbt_isa.c | ||
| 156 ↗ | (On Diff #6010) | Why are you searching for ldp and not ret? |
| cddl/contrib/opensolaris/lib/libdtrace/common/dt_link.c | ||
|---|---|---|
| 230–235 ↗ | (On Diff #6194) | What do we need to do here (for arm/mips in general, not just aarch64)? |
| 432–437 ↗ | (On Diff #6194) | and what do we need to do here? |
| lib/libproc/proc_regs.c | ||
| 62 ↗ | (On Diff #6194) | Yes, I'd like to see this committed as is. The aarch64 #ifs should be resorted to be first though to keep alpha order. |
| lib/libproc/proc_bkpt.c | ||
|---|---|---|
| 58 ↗ | (On Diff #6194) | |
| cddl/contrib/opensolaris/lib/libdtrace/common/dt_link.c | ||
|---|---|---|
| 233 ↗ | (On Diff #6332) | This should be in alphabetical order, aarch64 should be before arm. |
| 434 ↗ | (On Diff #6332) | And this |
| 839 ↗ | (On Diff #6332) | And this |
| cddl/lib/Makefile | ||
| 31 ↗ | (On Diff #6332) | This should be sorted, it was missed when arm was added, but that shouldn't mean we do the same with AArch64. |
| cddl/lib/libdtrace/Makefile | ||
| 89 ↗ | (On Diff #6332) | Alphabetical |
| lib/Makefile | ||
| 220 ↗ | (On Diff #6332) | Alphabetical |
| lib/libproc/proc_bkpt.c | ||
| 54 ↗ | (On Diff #6332) | Alphabetical |
| 55 ↗ | (On Diff #6332) | Can you use a different brk value? It might also pay to document them on the wiki. |
| sys/arm64/arm64/trap.c | ||
| 267 ↗ | (On Diff #6332) | You should also check the breakpoint instruction has the correct value so we don't hit the ddb brk. |
| sys/cddl/dev/dtrace/aarch64/dtrace_asm.S | ||
| 156–157 ↗ | (On Diff #6332) | Why not replace these two instructions with cbnz? |
| 171–172 ↗ | (On Diff #6332) | And here |
| sys/cddl/dev/fbt/aarch64/fbt_isa.c | ||
| 43 ↗ | (On Diff #6332) | This should be a unique value in the EL1 range. |
| 116 ↗ | (On Diff #6332) | Does this function exist on arm64? |
| 123 ↗ | (On Diff #6332) | This list should be checked in some central location. |
| 167 ↗ | (On Diff #6332) | There is no branch delay slot on arm. It's also a bug in the 32-bit dtrace code. |
| 195 ↗ | (On Diff #6332) | POPM? Shouldn't it be named DTRACE_INVOP_RET? |
| lib/libproc/proc_bkpt.c | ||
|---|---|---|
| 58 ↗ | (On Diff #6429) | So I set 0x14 for libproc and 0x40d for dtrace |
| 55 ↗ | (On Diff #6332) | I have set 20 as BRK value. See BREAKPOINT_INSTR define |
| sys/cddl/dev/fbt/aarch64/fbt_isa.c | ||
| 44 ↗ | (On Diff #6429) | Ok let it be 0x40d |
| 117 ↗ | (On Diff #6429) | not sure |
| 124 ↗ | (On Diff #6429) | what you mean? |
| 168 ↗ | (On Diff #6429) | right, thanks |