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Differential D12848

Remove 'adding_user.7'
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Authored by eadler on Oct 31 2017, 11:49 AM.
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allanjude
editor_callfortesting.org
imp

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manpages
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rS325257: Remove 'adding_user.7'
Summary

Not to be confused with adduser.
Not to be confused with useful information.

Diff Detail

Repository
rS FreeBSD src repository - subversion
Lint
Lint Passed
Unit
No Test Coverage
Build Status
Buildable 12325
Build 12614: arc lint + arc unit

Event Timeline

eadler created this revision.Oct 31 2017, 11:49 AM
Herald added a reviewer: manpages. · View Herald TranscriptOct 31 2017, 11:49 AM
Herald added a subscriber: imp. · View Herald Transcript
Harbormaster completed remote builds in B12325: Diff 34501.Oct 31 2017, 11:49 AM
allanjude added a subscriber: allanjude.Oct 31 2017, 11:50 AM

Did you check for other man pages that .Xr this manpage?

eadler added a comment.Oct 31 2017, 11:55 AM

good call. I checked in share but forgot about the obvious...

eadler updated this revision to Diff 34503.Oct 31 2017, 11:56 AM

also grab adduser Xr

Harbormaster completed remote builds in B12327: Diff 34503.Oct 31 2017, 11:56 AM
Closed by commit rS325257: Remove 'adding_user.7' (authored by eadler). · Explain WhyNov 1 2017, 1:22 AM
This revision was automatically updated to reflect the committed changes.
editor_callfortesting.org added a subscriber: editor_callfortesting.org.Nov 3 2017, 5:56 AM

Were the tips removed by this added to adduser(8) or the Handbook?

eadler added a comment.Nov 3 2017, 6:00 AM
In D12848#268319, @editor_callfortesting.org wrote:

Were the tips removed by this added to adduser(8) or the Handbook?

They were either already in the handbook or wrong.

Revision Contents
Changeset List

PathSize
2 lines
share/
man/
man7/
3 lines

Diff 34501

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ObsoleteFiles.inc

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
#include <sys/cpuset.h> #include <sys/cpuset.h>
#include <sys/lock.h> #include <sys/lock.h>
#include <sys/mutex.h> #include <sys/mutex.h>
#include <vm/vm.h> #include <vm/vm.h>
#include <vm/pmap.h> #include <vm/pmap.h>
#include <machine/bus.h> #include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/intr.h> #include <machine/intr.h>
#include "pic_if.h" #include "pic_if.h"
#include "gic_v3_reg.h" #include "gic_v3_reg.h"
#include "gic_v3_var.h" #include "gic_v3_var.h"
/* Device and PIC methods */ /* Device and PIC methods */
▲ Show 20 Lines • Show All 166 Lines • ▼ Show 20 Lines
* PIC interface. * PIC interface.
*/ */
static void static void
gic_v3_dispatch(device_t dev, struct trapframe *frame) gic_v3_dispatch(device_t dev, struct trapframe *frame)
{ {
uint64_t active_irq; uint64_t active_irq;
while (1) { while (1) {
if (CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1) {
/*
* Hardware: Cavium ThunderX
* Chip revision: Pass 1.0, Pass 1.1
* ERRATUM: 22978, 23154
impUnsubmitted
Not Done
Inline Actions

So both Pass 1.0 and 1.1 have this errata. Is Cavium really going to market with Pass 1.1? that likely means we'd have to keep this around for a long time. If that's just the first wave and there will be a Pass 2.0 which fixes this, that would be better.

imp: So both Pass 1.0 and 1.1 have this errata. Is Cavium really going to market with Pass 1.1? that…
emasteUnsubmitted
Not Done
Inline Actions

As far as we know right now, yes.

emaste: As far as we know right now, yes.
*/
__asm __volatile("nop;nop;nop;nop;nop;nop;nop;nop;\n"
"mrs %0, ICC_IAR1_EL1\n"
"nop;nop;nop;nop;dsb sy;" : "=&r" (active_irq));
} else {
active_irq = gic_icc_read(IAR1); active_irq = gic_icc_read(IAR1);
andrewUnsubmitted
Not Done
Inline Actions

Quoting https://lkml.org/lkml/2015/7/6/247

If you need an instruction sequence to be consecutive, then it _must_
be one single asm().

I would also like a comment explaining why all the nops are needed, and on what hardware the errata applies to. There have been a few places with other architectures where they needed a collection of nops, but nobody can remember why, or knew if they are still needed.

andrew: Quoting https://lkml.org/lkml/2015/7/6/247 If you need an instruction sequence to be…
wma_semihalf.comAuthorUnsubmitted
Not Done
Inline Actions

Fixed, comments added. Unfortunately, these are the only information than can go public.

wma_semihalf.com: Fixed, comments added. Unfortunately, these are the only information than can go public.
emasteUnsubmitted
Not Done
Inline Actions

Is it possible to expand on the meaning of Pass 1.0/1.1?

emaste: Is it possible to expand on the meaning of `Pass 1.0/1.1`?
}
if (__predict_false(active_irq == ICC_IAR1_EL1_SPUR)) if (__predict_false(active_irq == ICC_IAR1_EL1_SPUR))
break; break;
if (__predict_true((active_irq >= GIC_FIRST_PPI && if (__predict_true((active_irq >= GIC_FIRST_PPI &&
active_irq <= GIC_LAST_SPI) || active_irq >= GIC_FIRST_LPI)) { active_irq <= GIC_LAST_SPI) || active_irq >= GIC_FIRST_LPI)) {
arm_dispatch_intr(active_irq, frame); arm_dispatch_intr(active_irq, frame);
continue; continue;
▲ Show 20 Lines • Show All 342 Lines • Show Last 20 Lines
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share/man/man7/Makefile

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
#include <sys/cpuset.h> #include <sys/cpuset.h>
#include <sys/lock.h> #include <sys/lock.h>
#include <sys/mutex.h> #include <sys/mutex.h>
#include <vm/vm.h> #include <vm/vm.h>
#include <vm/pmap.h> #include <vm/pmap.h>
#include <machine/bus.h> #include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/intr.h> #include <machine/intr.h>
#include "pic_if.h" #include "pic_if.h"
#include "gic_v3_reg.h" #include "gic_v3_reg.h"
#include "gic_v3_var.h" #include "gic_v3_var.h"
/* Device and PIC methods */ /* Device and PIC methods */
▲ Show 20 Lines • Show All 166 Lines • ▼ Show 20 Lines
* PIC interface. * PIC interface.
*/ */
static void static void
gic_v3_dispatch(device_t dev, struct trapframe *frame) gic_v3_dispatch(device_t dev, struct trapframe *frame)
{ {
uint64_t active_irq; uint64_t active_irq;
while (1) { while (1) {
if (CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1) {
/*
* Hardware: Cavium ThunderX
* Chip revision: Pass 1.0, Pass 1.1
* ERRATUM: 22978, 23154
impUnsubmitted
Not Done
Inline Actions

So both Pass 1.0 and 1.1 have this errata. Is Cavium really going to market with Pass 1.1? that likely means we'd have to keep this around for a long time. If that's just the first wave and there will be a Pass 2.0 which fixes this, that would be better.

imp: So both Pass 1.0 and 1.1 have this errata. Is Cavium really going to market with Pass 1.1? that…
emasteUnsubmitted
Not Done
Inline Actions

As far as we know right now, yes.

emaste: As far as we know right now, yes.
*/
__asm __volatile("nop;nop;nop;nop;nop;nop;nop;nop;\n"
"mrs %0, ICC_IAR1_EL1\n"
"nop;nop;nop;nop;dsb sy;" : "=&r" (active_irq));
} else {
active_irq = gic_icc_read(IAR1); active_irq = gic_icc_read(IAR1);
andrewUnsubmitted
Not Done
Inline Actions

Quoting https://lkml.org/lkml/2015/7/6/247

If you need an instruction sequence to be consecutive, then it _must_
be one single asm().

I would also like a comment explaining why all the nops are needed, and on what hardware the errata applies to. There have been a few places with other architectures where they needed a collection of nops, but nobody can remember why, or knew if they are still needed.

andrew: Quoting https://lkml.org/lkml/2015/7/6/247 If you need an instruction sequence to be…
wma_semihalf.comAuthorUnsubmitted
Not Done
Inline Actions

Fixed, comments added. Unfortunately, these are the only information than can go public.

wma_semihalf.com: Fixed, comments added. Unfortunately, these are the only information than can go public.
emasteUnsubmitted
Not Done
Inline Actions

Is it possible to expand on the meaning of Pass 1.0/1.1?

emaste: Is it possible to expand on the meaning of `Pass 1.0/1.1`?
}
if (__predict_false(active_irq == ICC_IAR1_EL1_SPUR)) if (__predict_false(active_irq == ICC_IAR1_EL1_SPUR))
break; break;
if (__predict_true((active_irq >= GIC_FIRST_PPI && if (__predict_true((active_irq >= GIC_FIRST_PPI &&
active_irq <= GIC_LAST_SPI) || active_irq >= GIC_FIRST_LPI)) { active_irq <= GIC_LAST_SPI) || active_irq >= GIC_FIRST_LPI)) {
arm_dispatch_intr(active_irq, frame); arm_dispatch_intr(active_irq, frame);
continue; continue;
▲ Show 20 Lines • Show All 342 Lines • Show Last 20 Lines
View Options

share/man/man7/adding_user.7

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
#include <sys/cpuset.h> #include <sys/cpuset.h>
#include <sys/lock.h> #include <sys/lock.h>
#include <sys/mutex.h> #include <sys/mutex.h>
#include <vm/vm.h> #include <vm/vm.h>
#include <vm/pmap.h> #include <vm/pmap.h>
#include <machine/bus.h> #include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/intr.h> #include <machine/intr.h>
#include "pic_if.h" #include "pic_if.h"
#include "gic_v3_reg.h" #include "gic_v3_reg.h"
#include "gic_v3_var.h" #include "gic_v3_var.h"
/* Device and PIC methods */ /* Device and PIC methods */
▲ Show 20 Lines • Show All 166 Lines • ▼ Show 20 Lines
* PIC interface. * PIC interface.
*/ */
static void static void
gic_v3_dispatch(device_t dev, struct trapframe *frame) gic_v3_dispatch(device_t dev, struct trapframe *frame)
{ {
uint64_t active_irq; uint64_t active_irq;
while (1) { while (1) {
if (CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1) {
/*
* Hardware: Cavium ThunderX
* Chip revision: Pass 1.0, Pass 1.1
* ERRATUM: 22978, 23154
impUnsubmitted
Not Done
Inline Actions

So both Pass 1.0 and 1.1 have this errata. Is Cavium really going to market with Pass 1.1? that likely means we'd have to keep this around for a long time. If that's just the first wave and there will be a Pass 2.0 which fixes this, that would be better.

imp: So both Pass 1.0 and 1.1 have this errata. Is Cavium really going to market with Pass 1.1? that…
emasteUnsubmitted
Not Done
Inline Actions

As far as we know right now, yes.

emaste: As far as we know right now, yes.
*/
__asm __volatile("nop;nop;nop;nop;nop;nop;nop;nop;\n"
"mrs %0, ICC_IAR1_EL1\n"
"nop;nop;nop;nop;dsb sy;" : "=&r" (active_irq));
} else {
active_irq = gic_icc_read(IAR1); active_irq = gic_icc_read(IAR1);
andrewUnsubmitted
Not Done
Inline Actions

Quoting https://lkml.org/lkml/2015/7/6/247

If you need an instruction sequence to be consecutive, then it _must_
be one single asm().

I would also like a comment explaining why all the nops are needed, and on what hardware the errata applies to. There have been a few places with other architectures where they needed a collection of nops, but nobody can remember why, or knew if they are still needed.

andrew: Quoting https://lkml.org/lkml/2015/7/6/247 If you need an instruction sequence to be…
wma_semihalf.comAuthorUnsubmitted
Not Done
Inline Actions

Fixed, comments added. Unfortunately, these are the only information than can go public.

wma_semihalf.com: Fixed, comments added. Unfortunately, these are the only information than can go public.
emasteUnsubmitted
Not Done
Inline Actions

Is it possible to expand on the meaning of Pass 1.0/1.1?

emaste: Is it possible to expand on the meaning of `Pass 1.0/1.1`?
}
if (__predict_false(active_irq == ICC_IAR1_EL1_SPUR)) if (__predict_false(active_irq == ICC_IAR1_EL1_SPUR))
break; break;
if (__predict_true((active_irq >= GIC_FIRST_PPI && if (__predict_true((active_irq >= GIC_FIRST_PPI &&
active_irq <= GIC_LAST_SPI) || active_irq >= GIC_FIRST_LPI)) { active_irq <= GIC_LAST_SPI) || active_irq >= GIC_FIRST_LPI)) {
arm_dispatch_intr(active_irq, frame); arm_dispatch_intr(active_irq, frame);
continue; continue;
▲ Show 20 Lines • Show All 342 Lines • Show Last 20 Lines