The bwn(4) driver requires a number of extensions to our PMU/PWRCTL APIs to support external
configuration of PLLs, LDOs, and other parameters that require chipset or PHY-specific
workarounds.

This diff introduces all PMU-related improvements required for bwn(4), with support for:

• Writing raw voltage register values to PHY-specific LDO regulator registers (required by LP-PHY).
• Enabling/disabling PHY-specific LDOs (required by LP-PHY)
• Writing to arbitrary PMU chipctrl registers (required for common PHY PLL reset support).
• Requesting chipset/PLL-specific ``spuravoid'' (spurious signal avoidance) modes.
• Querying clock frequency and latency.

Rather than updating legacy PWRCTL support to conform to the new PMU interface, I've lifted
PWRCTL support out of the bhnd(4) bus implementation entirely:

• PWRCTL API is now provided by the bhnd_pwrctl_if.m interface.
• The host bridge PWRCTL clock gating APIs in bhnd_bus_if.m have been lifted out into a new bhnd_pwrctl_hostb_if.m interface.
• Since PWRCTL is only found in older SSB-based chipsets, translation from bhnd(4) bus APIs to corresponding PWRCTL operations is now handled entirely within the siba(4) driver. This simplifies the bcma(4), bhnd(4), and bhnd_pmu(4) driver implementations.

Depends on D12518, D12582

Tested against bcma(4) and siba(4) MIPS targets, with no regressions found.

Tested against bwn(4) PCIe devices (using the in-development bhnd compatibility shims).