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Implement MIPS and PCI(e) interrupt support.
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Authored by landonf on Sep 27 2017, 10:04 PM.

Details

Summary

On BHND MIPS SoCs, this replaces the use of hard-coded non-portable MIPS CPU
IRQs in the common bhnd(4) core drivers; we now register an INTRNG child PIC
that handles routing of backplane interrupt signals to the MIPS core, where
they are mapped to MIPS CPU interrupts and dispatched accordingly.

Dedicated MIPS CPU interrupts are allocated according to a simple core priority
table, with a single shared MIPS CPU interrupt reserved for lower-priority
cores.

On BHND PCIe devices, backplane interrupt signals are now routed to the PCI/PCIe
host bridge core when bus_setup_intr() is called, where they are dispatched by
the PCI core via a host interrupt (e.g. INTx/MSI/MSI-X on PCI bridge cores).

The bhndb(4) bridge driver tracks registered interrupt handlers for the bridged
bhnd(4) devices, delegating actual interrupt setup/teardown to the parent PCI
bus on behalf of the bridged cores.

Depends on D12385

Test Plan

Tested against bcma(4) and siba(4) MIPS targets, with no regressions found in
the existing bhnd(4) drivers that make use of interrupts (bhnd_usb(4),
bhnd_chipc(4)).

Tested against bwn(4) PCIe devices (using the in-development bhnd compatibility shims),
and verified that the MAC core's interrupts are correctly dispatched to the
bwn(4) driver's interrupt handler.

Diff Detail

Repository
rS FreeBSD src repository
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Event Timeline

landonf created this revision.Sep 27 2017, 10:04 PM
landonf updated this revision to Diff 33579.Sep 30 2017, 12:47 AM

Re-enable support for the PCIe-G2 core.

mizhka_gmail.com added inline comments.
sys/mips/broadcom/bcm_mips74k.c
311–332 ↗(On Diff #33579)

May be single bus_read_4 is enough thanks to fixed step between registers?

sys/mips/broadcom/bcma_nexus.c
62 ↗(On Diff #33579)

typo, BMCA

sys/mips/include/intr.h
62–63 ↗(On Diff #33579)

in intr_machdep.h it's defined for !(defined(CPU_RMI) || defined(CPU_NLM)).

landonf added inline comments.Nov 10 2017, 7:10 PM
sys/mips/include/intr.h
62–63 ↗(On Diff #33579)

I could do the same here, but these are only defined if INTRNG is enabled; mips/rmi and mips/nlm will already need to make changes to intr.h and mips_pic.c if/when they adopt INTRNG (and it's possible they never will), so I'd prefer to avoid preemptively including changes that imply support for RMI/NLM that doesn't actually exist.

landonf updated this revision to Diff 35053.Nov 10 2017, 8:26 PM
  • Simplify IRQ switch() statement by using BCM_MIPS74K_INTR_SEL(irq).
  • Fix BMCA->BCMA typo.
landonf marked 3 inline comments as done.Nov 10 2017, 8:26 PM
This revision was automatically updated to reflect the committed changes.