On BHND MIPS SoCs, this replaces the use of hard-coded non-portable MIPS CPU
IRQs in the common bhnd(4) core drivers; we now register an INTRNG child PIC
that handles routing of backplane interrupt signals to the MIPS core, where
they are mapped to MIPS CPU interrupts and dispatched accordingly.

Dedicated MIPS CPU interrupts are allocated according to a simple core priority
table, with a single shared MIPS CPU interrupt reserved for lower-priority
cores.

On BHND PCIe devices, backplane interrupt signals are now routed to the PCI/PCIe
host bridge core when bus_setup_intr() is called, where they are dispatched by
the PCI core via a host interrupt (e.g. INTx/MSI/MSI-X on PCI bridge cores).

The bhndb(4) bridge driver tracks registered interrupt handlers for the bridged
bhnd(4) devices, delegating actual interrupt setup/teardown to the parent PCI
bus on behalf of the bridged cores.

Depends on D12385

Tested against bcma(4) and siba(4) MIPS targets, with no regressions found in
the existing bhnd(4) drivers that make use of interrupts (bhnd_usb(4),
bhnd_chipc(4)).

Tested against bwn(4) PCIe devices (using the in-development bhnd compatibility shims),
and verified that the MAC core's interrupts are correctly dispatched to the
bwn(4) driver's interrupt handler.