Add eswin reset driver
Details
Details
- Reviewers
mhorne jrtc27 - Commits
- rG56816e687557: riscv: Eswin hwreset support added.
Works on SiFive Premier P550
Diff Detail
Diff Detail
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Event Timeline
sys/riscv/eswin/eswin_reset.c | ||
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170 | Why not just use IDs from 0 through N? You can then do >> 5 to get the word number and & 31 to get the bit offset. That's really how the FDT should have represented it too, probably... logically it's just a big bit vector. |
sys/riscv/eswin/eswin_reset.c | ||
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165 | << 5 but & 0xff is inconsistent and not what I said (which was & 31 ie 0x1f). Also is cells[1] the bit number or bit mask? Because it's being encoded as if it's the former, but used in the other functions as if it's the latter (no 1u << bit). |
sys/riscv/eswin/eswin_reset.c | ||
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51 | Unused? |