This uart has the requirement for 32-bit sized and aligned memory
accesses. It is also described in the Serial Port Console Redirection
Table (SPCR) with a different interface type value.
Sponsored by: Arm Ltd
Differential D45834 Authored by andrew on Jul 2 2024, 4:38 PM.
Details Summary This uart has the requirement for 32-bit sized and aligned memory Sponsored by: Arm Ltd
Diff Detail
Event Timelineandrew created this revision. Harbormaster completed remote builds in B58451: Diff 140469.Jul 2 2024, 4:38 PM2024-07-02 16:38:36 (UTC+0) This revision is now accepted and ready to land.Jul 3 2024, 4:06 AM2024-07-03 04:06:52 (UTC+0) Closed by commit rG9840598aa31f: dev/uart: Add APMC0D08 as found in the Intel E2100 (authored by andrew). · Explain WhyJul 23 2024, 9:52 AM2024-07-23 09:52:35 (UTC+0) This revision was automatically updated to reflect the committed changes.
Revision Contents
Diff 140469 sys/dev/uart/uart_dev_ns8250.c
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Should this size be macro-ized?